Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system

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Islam S.Z.
Ali M.A.M.
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Institution of Engineers (Australia)
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The optimisation of combined built-in self-test (BIST) and automatic test equipment (ATE) is desirable for complex fabricated chip testing to meet the high fault coverage while preserving acceptable costs. The fault coverage of BIST and ATE plays a significant role, because it can affect the area overhead in BIST and the test time in BIST/ATE. In this paper, a test circuit system (TCS) employing the hybrid technique (combined BIST/ATE) of test pattern generation is presented. The very large scale integration (VLSI) circuit testing features of the hybrid technique overcome the requirements for expensive ATE, as well as extra silicon area in BIST applications. The extendable input/output bus and IDDQ features for the TCS are also shown to enhance the testing capacity corresponding to recent VLSI circuit and system-on-chip requirements. � Institution of Engineers Australia, 2010.
Automatic testing , Equipment testing , Integrated circuit testing , Integration testing , Mixed signal integrated circuits , Reconfigurable hardware , Semiconductor device manufacture , System-on-chip , Timing circuits , VLSI circuits , Automatic test equipment , Circuit testing , Fabricated chips , Fault coverages , Hybrid techniques , Reconfigurable , Test pattern generations , Very-large-scale integration circuits , Built-in self test