Publication: Modeling, simulation and optimization of 14nm high-K/metal gate NMOS with taguchi method
Date
2018
Authors
Mah S.K.
Ahmad I.
Ker P.J.
Tan K.P.
Faizah Z.A.N.
Journal Title
Journal ISSN
Volume Title
Publisher
Institute of Electrical and Electronics Engineers Inc.
Abstract
The developments in electronics technology push the invention of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) towards smaller physical dimension with improvements in both quality and performance. In this paper, design, fabrication and simulation of electrical characteristics of 14nm La2O3/WSi2NMOS is presented. The fabrication and simulation process of device were performed by using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools, which consists of ATHENA and ATLAS. The designed device was optimized using Taguchi Method that involves orthogonal arrays and analysis of variance (ANOVA). The original results before optimization process for VTHis 0.212648V (7.5% lower than the targeted value) and IOFF is 3.73851�10-9 A/?m while the optimized results for VTH is 0.233321 V (1.44 % higher than the targeted value) and IOFFis 4.732375�10-11 A/?m which fulfilled the targets based on International Technology Roadmap for Semiconductors (ITRS) 2013. The Taguchi optimization method yields a significantly lower IOFF with an improved ION/IOFF ratio by a factor of 25. � 2018 IEEE.
Description
Analysis of variance (ANOVA); Electron beam lithography; Metals; MOS devices; Oxide semiconductors; Taguchi methods; ATHENA; ATLAS; Electrical characteristic; Electronics technology; International Technology Roadmap for Semiconductors; MOS-FET; Simulation and optimization; Taguchi optimization method; MOSFET devices