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Modeling, simulation and optimization of 14nm high-K/metal gate NMOS with taguchi method

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dc.citedby2
dc.contributor.authorMah S.K.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorKer P.J.en_US
dc.contributor.authorTan K.P.en_US
dc.contributor.authorFaizah Z.A.N.en_US
dc.contributor.authorid57191706660en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid37461740800en_US
dc.contributor.authorid57204581058en_US
dc.contributor.authorid56395444600en_US
dc.date.accessioned2023-05-29T06:50:51Z
dc.date.available2023-05-29T06:50:51Z
dc.date.issued2018
dc.descriptionAnalysis of variance (ANOVA); Electron beam lithography; Metals; MOS devices; Oxide semiconductors; Taguchi methods; ATHENA; ATLAS; Electrical characteristic; Electronics technology; International Technology Roadmap for Semiconductors; MOS-FET; Simulation and optimization; Taguchi optimization method; MOSFET devicesen_US
dc.description.abstractThe developments in electronics technology push the invention of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) towards smaller physical dimension with improvements in both quality and performance. In this paper, design, fabrication and simulation of electrical characteristics of 14nm La2O3/WSi2NMOS is presented. The fabrication and simulation process of device were performed by using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools, which consists of ATHENA and ATLAS. The designed device was optimized using Taguchi Method that involves orthogonal arrays and analysis of variance (ANOVA). The original results before optimization process for VTHis 0.212648V (7.5% lower than the targeted value) and IOFF is 3.73851�10-9 A/?m while the optimized results for VTH is 0.233321 V (1.44 % higher than the targeted value) and IOFFis 4.732375�10-11 A/?m which fulfilled the targets based on International Technology Roadmap for Semiconductors (ITRS) 2013. The Taguchi optimization method yields a significantly lower IOFF with an improved ION/IOFF ratio by a factor of 25. � 2018 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo8481293
dc.identifier.doi10.1109/SMELEC.2018.8481293
dc.identifier.epage278
dc.identifier.scopus2-s2.0-85056258752
dc.identifier.spage275
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85056258752&doi=10.1109%2fSMELEC.2018.8481293&partnerID=40&md5=f1f779dfeebb3a2123e1c26b69f3267e
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/23663
dc.identifier.volume2018-August
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceScopus
dc.sourcetitleIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
dc.titleModeling, simulation and optimization of 14nm high-K/metal gate NMOS with taguchi methoden_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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