Publication: Optimization of reflow profile for copper pillar with SAC305 solder cap FCCSP
No Thumbnail Available
Date
2023
Authors
Zainudin W.Z.Z.W.
Yong T.C.
Hui T.C.
Kar Y.B.
Hoong W.Y.
Journal Title
Journal ISSN
Volume Title
Publisher
Springer
Abstract
The current trend of electrical devices development is progressing towards miniaturization, multi-function and high density, device integration and fine pitch in a smaller package size. This led to the invention of copper pillar bumps which acts as a connection between the dies to its corresponding substrate, which allows the fabrication of smaller semiconductor devices. The dies were mounted onto the substrate by undergoing mass reflow process where the SAC305 solder from the copper pillar bumps and substrate bumps will melt together and solidify to form a solder joint. The quality of the solder joint is influenced by the parameters that govern the reflow profile, which are ramp rate, soak time, time above liquidus time, peak temperature and cooling rate. If the reflow profile is not properly optimized, defects such as voids in the solder joint can pose a reliability issue for the packaged unit. Therefore, in this paper, ramp rate, soak time and time above liquidus of reflow profiles for die utilizing copper pillar bumps with SAC305 as its solder material was studied and optimized in finding the recommended range of each parameter of the reflow profiles that yield the least voiding in the solder joint. The experiment was conducted by varying the reflow profile parameter which are ramp rate, soak time and time above liquidus, which the solder joint cross section and X-ray images were then analysed to study its influences. Additional experiment that investigates flux outgassing rate of different flux activity levels and the influence of component standoff height and mis-alignment offset towards solder-creeping defect were conducted in this article. � 2023, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
Description
Keywords
Chip scale packages , Copper , Defects , Flip chip devices , Soldering , 'current , Copper pillars , Device development , Electrical devices , Liquidus , Miniaturisation , Optimisations , Ramp-rate , Soak time , Solder joints , Substrates