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Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA

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dc.citedby11
dc.contributor.authorShahadi H.I.en_US
dc.contributor.authorJidin R.en_US
dc.contributor.authorWay W.H.en_US
dc.contributor.authorid54956597100en_US
dc.contributor.authorid6508169028en_US
dc.contributor.authorid55936039400en_US
dc.date.accessioned2023-05-29T06:14:11Z
dc.date.available2023-05-29T06:14:11Z
dc.date.issued2016
dc.descriptionComputer architecture; Field programmable gate arrays (FPGA); Hardware; Parallel processing systems; Programmable logic controllers; Signal to noise ratio; Steganography; Wavelet transforms; Audio steganography; Dual modes; Field programmable logic; Lifting wavelet transforms; Security; Computer hardware description languagesen_US
dc.description.abstractRecently, audio steganography has become an important covert communications technology. This technology hides secret data in a cover audio without perceptual modification of the cover audio. Most of the existing audio steganography techniques are unsuitable for real-time communication. Although field programmable logic array (FPGA) technologies offer parallel processing in hardware that can improve the speed of steganographic systems, the research activities in this area are very limited. This paper presents a parallel hardware-architecture for dual-mode audio steganography (DMAS) based FPGA technology. The proposed DMAS reconfigures the same hardware blocks in both hiding and recovery modes to reduce the hardware requirements. It has been successfully implemented on a Xilinx XC6SLX16 FPGA board to occupy only 97 slices. Furthermore, it processes data simultaneously at an operating frequency of up to 58.82 MHz and accomplishes full message retrieval at an embedding rate of 25% with an audio quality above 45 dB in terms of signal to noise ratio. � 2015 Elsevier Ltd . All rights reserved.en_US
dc.description.natureFinalen_US
dc.identifier.doi10.1016/j.compeleceng.2015.03.007
dc.identifier.epage116
dc.identifier.scopus2-s2.0-84925703518
dc.identifier.spage95
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84925703518&doi=10.1016%2fj.compeleceng.2015.03.007&partnerID=40&md5=26262df9f5e89d8b71cd08c46edf646d
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/23013
dc.identifier.volume49
dc.publisherElsevier Ltden_US
dc.sourceScopus
dc.sourcetitleComputers and Electrical Engineering
dc.titleConcurrent hardware architecture for dual-mode audio steganography processor-based FPGAen_US
dc.typeArticleen_US
dspace.entity.typePublication
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