Publication: Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA
Date
2016
Authors
Shahadi H.I.
Jidin R.
Way W.H.
Journal Title
Journal ISSN
Volume Title
Publisher
Elsevier Ltd
Abstract
Recently, audio steganography has become an important covert communications technology. This technology hides secret data in a cover audio without perceptual modification of the cover audio. Most of the existing audio steganography techniques are unsuitable for real-time communication. Although field programmable logic array (FPGA) technologies offer parallel processing in hardware that can improve the speed of steganographic systems, the research activities in this area are very limited. This paper presents a parallel hardware-architecture for dual-mode audio steganography (DMAS) based FPGA technology. The proposed DMAS reconfigures the same hardware blocks in both hiding and recovery modes to reduce the hardware requirements. It has been successfully implemented on a Xilinx XC6SLX16 FPGA board to occupy only 97 slices. Furthermore, it processes data simultaneously at an operating frequency of up to 58.82 MHz and accomplishes full message retrieval at an embedding rate of 25% with an audio quality above 45 dB in terms of signal to noise ratio. � 2015 Elsevier Ltd . All rights reserved.
Description
Computer architecture; Field programmable gate arrays (FPGA); Hardware; Parallel processing systems; Programmable logic controllers; Signal to noise ratio; Steganography; Wavelet transforms; Audio steganography; Dual modes; Field programmable logic; Lifting wavelet transforms; Security; Computer hardware description languages