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LFSR based fast seed selection technique reducing test time of I DDQ testing

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dc.citedby1
dc.contributor.authorIslam S.Z.en_US
dc.contributor.authorJidin R.B.en_US
dc.contributor.authorAli M.A.M.en_US
dc.contributor.authorid55432804400en_US
dc.contributor.authorid6508169028en_US
dc.contributor.authorid6507416666en_US
dc.date.accessioned2023-12-29T07:52:10Z
dc.date.available2023-12-29T07:52:10Z
dc.date.issued2009
dc.description.abstractThis paper proposed IDDQ testing of combinational circuit using Linear Feedback Shift Register (LFSR) based fast seed selection technique. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing. To reduce test time of IDDQ testing, bit-flipping technique is integrated with LFSR to reduce lower to higher (L to H) switching activities for combinational circuits. Experimental results for ISCAS'85 and ISCAS'89 benchmark circuits show the effectiveness (7% improvement) of the technique for reducing testing time delay. � 2009 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo5356430
dc.identifier.doi10.1109/ISIEA.2009.5356430
dc.identifier.epage364
dc.identifier.scopus2-s2.0-76449108054
dc.identifier.spage362
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-76449108054&doi=10.1109%2fISIEA.2009.5356430&partnerID=40&md5=71631f52a949de98a4dcd45dc30c57da
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/30737
dc.identifier.volume1
dc.pagecount2
dc.sourceScopus
dc.sourcetitle2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings
dc.subjectBridging fault
dc.subjectI<sub>DDQ</sub>
dc.subjectLFSR
dc.subjectCombinatorial circuits
dc.subjectIndustrial electronics
dc.subjectShift registers
dc.subjectBenchmark circuit
dc.subjectBit flipping
dc.subjectBridging fault
dc.subjectCMOS circuits
dc.subjectCombinational circuits
dc.subjectIDDQ testing
dc.subjectLinear feedback shift registers
dc.subjectLogic testing
dc.subjectSeed selection
dc.subjectSwitching activities
dc.subjectTest time
dc.subjectTesting time
dc.subjectDelay circuits
dc.titleLFSR based fast seed selection technique reducing test time of I DDQ testingen_US
dc.typeConference paperen_US
dspace.entity.typePublication
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