Publication: LFSR based fast seed selection technique reducing test time of I DDQ testing
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Date
2009
Authors
Islam S.Z.
Jidin R.B.
Ali M.A.M.
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Abstract
This paper proposed IDDQ testing of combinational circuit using Linear Feedback Shift Register (LFSR) based fast seed selection technique. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing. To reduce test time of IDDQ testing, bit-flipping technique is integrated with LFSR to reduce lower to higher (L to H) switching activities for combinational circuits. Experimental results for ISCAS'85 and ISCAS'89 benchmark circuits show the effectiveness (7% improvement) of the technique for reducing testing time delay. � 2009 IEEE.
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Keywords
Bridging fault , I<sub>DDQ</sub> , LFSR , Combinatorial circuits , Industrial electronics , Shift registers , Benchmark circuit , Bit flipping , Bridging fault , CMOS circuits , Combinational circuits , IDDQ testing , Linear feedback shift registers , Logic testing , Seed selection , Switching activities , Test time , Testing time , Delay circuits