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Design and optimization of 22nm NMOS transistor

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dc.citedby14
dc.contributor.authorAfifah Maheran A.H.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorShaari S.en_US
dc.contributor.authorElgomati H.A.en_US
dc.contributor.authorMajlis B.Y.en_US
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorid36570222300en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid6603595092en_US
dc.contributor.authorid36536722700en_US
dc.contributor.authorid6603071546en_US
dc.contributor.authorid36239165300en_US
dc.date.accessioned2023-12-28T06:30:17Z
dc.date.available2023-12-28T06:30:17Z
dc.date.issued2012
dc.description.abstractIn this paper, we investigate the effects of four process parameters and two process noise parameters on the threshold voltage (V th) of a 22nm NMOS transistor. We used TiO 2 as the high-k material to replace the SiO 2 dielectric. The NMOS transistor was simulated using the fabrication tool ATHENA and electrical characterization was simulated using ATLAS. Taguchi's experimental design strategy was implemented with the L9 orthogonal array for conducting 36 simulation runs. The simulators were used for computing V th values for each row of the L9 array with 4 combinations of the 2 noise factors. The objective function for minimizing the variance in V th is achieved using Taguchi's nominal-the-best signal-to-noise ratio (SNR). Analysis of Mean (ANOM) was used to determine the best settings for the process parameters whereas. Analysis of variance (ANOVA) was used to reduce the variability of Vth. The best settings were used for verification experiments and the results show V th values with the least variance and that the mean value can be adjusted to 0.306V �0.027 for the 22nm NMOS, which is well within the ITRS2011 specifications.en_US
dc.description.natureFinalen_US
dc.identifier.epage8
dc.identifier.issue7
dc.identifier.scopus2-s2.0-84867909824
dc.identifier.spage1
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84867909824&partnerID=40&md5=1288beeeeb2cdaf1e9ef33212df51e1b
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29507
dc.identifier.volume6
dc.pagecount7
dc.sourceScopus
dc.sourcetitleAustralian Journal of Basic and Applied Sciences
dc.subject22nm NMOS
dc.subjectANOVA
dc.subjectOrthogonal array
dc.subjectTaguchi method
dc.subjectThreshold voltage
dc.titleDesign and optimization of 22nm NMOS transistoren_US
dc.typeArticleen_US
dspace.entity.typePublication
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