Publication:
Optimization of 16 nm DG-FinFET using L25 orthogonal array of Taguchi statistical method

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dc.citedby1
dc.contributor.authorRoslan A.F.en_US
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorZain A.S.M.en_US
dc.contributor.authorKaharudin K.E.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorid57203514087en_US
dc.contributor.authorid36239165300en_US
dc.contributor.authorid55925762500en_US
dc.contributor.authorid56472706900en_US
dc.contributor.authorid12792216600en_US
dc.date.accessioned2023-05-29T08:14:08Z
dc.date.available2023-05-29T08:14:08Z
dc.date.issued2020
dc.description.abstractThe impact of the optimization using Taguchi statistical method towards the electrical properties of a 16 nm double-gate FinFET (DG-FinFET) is investigated and analyzed. The inclusion of drive current (ION), leakage current (IOFF), and threshold voltage (VTH) as part of electrical properties presented in this paper will be determined by the amendment of six process parameters that comprises the polysilicon doping dose, polysilicon doping tilt, Source/Drain doping dose, Source/Drain doping tilt, VTH doping dose, VTH doping tilt, alongside the consideration of noise factor in gate oxidation temperature and polysilicon oxidation temperature. Silvaco TCAD software is utilized in this experiment with the employment of both ATHENA and ATLAS module to perform the respective device simulation and the electrical characterization of the device. The output responses obtained from the design is then succeeded by the implementation of Taguchi statistical method to facilitate the process parameter optimization as well as its design. The effectiveness of the process parameter is opted through the factor effect percentage on Signal-to-noise ratio with considerations towards ION and IOFF. The most dominant factor procured is the polysilicon doping tilt. The ION and IOFF obtained after the optimization are 1726.88 ?A/?m and 503.41 pA/?m for which has met the predictions of International Technology Roadmap for Semiconductors (ITRS) 2013. Copyright � 2020 Institute of Advanced Engineering and Science. All rights reserved.en_US
dc.description.natureFinalen_US
dc.identifier.doi10.11591/ijeecs.v18.i3.pp1207-1214
dc.identifier.epage1214
dc.identifier.issue3
dc.identifier.scopus2-s2.0-85079142293
dc.identifier.spage1207
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85079142293&doi=10.11591%2fijeecs.v18.i3.pp1207-1214&partnerID=40&md5=ba0d0e228fa97483b70951792ac8b9ad
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/25776
dc.identifier.volume18
dc.publisherInstitute of Advanced Engineering and Scienceen_US
dc.relation.ispartofAll Open Access, Gold, Green
dc.sourceScopus
dc.sourcetitleIndonesian Journal of Electrical Engineering and Computer Science
dc.titleOptimization of 16 nm DG-FinFET using L25 orthogonal array of Taguchi statistical methoden_US
dc.typeArticleen_US
dspace.entity.typePublication
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