Publication:
Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.

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dc.citedby2
dc.contributor.authorAfifah Maheran A.H.en_US
dc.contributor.authorFirhat E.N.en_US
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorMohd Zain A.S.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorNoor Faizah Z.A.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorElgomati H.A.en_US
dc.contributor.authorRoslan A.F.en_US
dc.contributor.authorid36570222300en_US
dc.contributor.authorid57217345087en_US
dc.contributor.authorid36239165300en_US
dc.contributor.authorid57217345950en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid56395444600en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid36536722700en_US
dc.contributor.authorid57203514087en_US
dc.date.accessioned2023-05-29T08:09:15Z
dc.date.available2023-05-29T08:09:15Z
dc.date.issued2020
dc.descriptionSilicides; Silicon on insulator technology; Taguchi methods; Current optimization; Device performance; Fabrication process; International technology; L9 orthogonal arrays; Performance parameters; Process parameters; Silicon-on- insulators (SOI); Hafnium oxidesen_US
dc.description.abstractTo acquire the optimal value of the performance parameter, a bilayer graphene with silicon on insulator (SOI) was enhanced and analyzed on 22 nm NMOS device. The device is made of Hafnium Dioxide (HfO2) as a high-k material whereas Tungsten Silicide (WSix) as a metal gate. The Silvaco software ATHENA and ATLAS modules were applied to simulate the fabrication process of virtual devices and to verify the device's electrical properties accordingly. The Taguchi L9 orthogonal array method was then used to enhance the device process parameters minimum leakage current (ILEAK) according to the International Technology Roadmap Semiconductor (ITRS) specification of 100nA/?m maximum range. The result from smaller-the-better (STB) for ILEAK is then reviewed by the percentage affecting the process parameter. The simulation result shows that the halo tilting angle is the most dominant factor for ILEAK optimization process. The optimized results indicate excellent device performance with ILEAK = 9.29746 nA/?m which is far lower than the prediction. � 2020 IOP Publishing Ltd. All rights reserved.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo12047
dc.identifier.doi10.1088/1742-6596/1502/1/012047
dc.identifier.issue1
dc.identifier.scopus2-s2.0-85087105139
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85087105139&doi=10.1088%2f1742-6596%2f1502%2f1%2f012047&partnerID=40&md5=8af66b405403bade61345faa52009bc5
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/25424
dc.identifier.volume1502
dc.publisherInstitute of Physics Publishingen_US
dc.relation.ispartofAll Open Access, Bronze
dc.sourceScopus
dc.sourcetitleJournal of Physics: Conference Series
dc.titleMinimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.en_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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