Publication:
Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array

Simple item page
dc.citedby7
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorHamid F.A.en_US
dc.contributor.authorZaharim A.en_US
dc.contributor.authorHamid A.M.A.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorElgomati H.A.en_US
dc.contributor.authorMajlis B.Y.en_US
dc.contributor.authorApte P.R.en_US
dc.contributor.authorid36239165300en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid6603573875en_US
dc.contributor.authorid15119466900en_US
dc.contributor.authorid36570222300en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid36536722700en_US
dc.contributor.authorid6603071546en_US
dc.contributor.authorid55725529100en_US
dc.date.accessioned2023-12-28T06:30:14Z
dc.date.available2023-12-28T06:30:14Z
dc.date.issued2012
dc.description.abstractIn this study, orthogonal array of L18 in Taguchi method was used to optimize the process parameters variance on threshold voltage (V TH) in 45nm p-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to study the performance characteristics of the PMOS device. There are eight process parameters (control factors) were varied for 2 and 3 levels to performed 18 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with L 18 Orthogonal Array to aid in design and optimize the process parameters. The predicted values of the process parameters were verified successfully with ATHENA and ATLAS's simulator. In PMOS device, VTH implant dose (26%) and compensate implant dose (26%) were the major factors affecting the threshold voltage. While S/D Implant was identified as an adjustment factor in PMOS device. These adjustment factors have been used to get the nominal values of threshold voltage for PMOS device closer to -0.289V. � 2012 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo6417127
dc.identifier.doi10.1109/SMElec.2012.6417127
dc.identifier.epage223
dc.identifier.scopus2-s2.0-84874123696
dc.identifier.spage219
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84874123696&doi=10.1109%2fSMElec.2012.6417127&partnerID=40&md5=f87fd96bcb96b278466f3e1adad88e5b
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29491
dc.pagecount4
dc.sourceScopus
dc.sourcetitle2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings
dc.subjectLeakage Current
dc.subjectNMOS Device
dc.subjectTaguchi Method
dc.subjectThreshold Voltage
dc.subjectElectron beam lithography
dc.subjectExperiments
dc.subjectLeakage currents
dc.subjectOptimization
dc.subjectSimulators
dc.subjectTaguchi methods
dc.subjectThreshold voltage
dc.subject3 levels
dc.subjectAdjustment factors
dc.subjectControl factors
dc.subjectDevice simulators
dc.subjectMajor factors
dc.subjectMOS-FET
dc.subjectNMOS devices
dc.subjectNoise factor
dc.subjectNominal values
dc.subjectOptimization of process parameters
dc.subjectOrthogonal array
dc.subjectP channels
dc.subjectPerformance characteristics
dc.subjectpMOS devices
dc.subjectProcess parameters
dc.subjectProcess simulators
dc.subjectSignal to noise (S/N) ratios
dc.subjectMOSFET devices
dc.titleOptimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal arrayen_US
dc.typeConference paperen_US
dspace.entity.typePublication
Files
Collections
SCOPUS