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Threshold voltage optimization in a 22nm High-k/Salicide PMOS device

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dc.citedby5
dc.contributor.authorAfifah Maheran A.H.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorYusoff Z.en_US
dc.contributor.authorid36570222300en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid19934514100en_US
dc.date.accessioned2023-12-28T04:13:04Z
dc.date.available2023-12-28T04:13:04Z
dc.date.issued2013
dc.description.abstractIn this article, we examine the effect of four process parameters and two noise parameters on the threshold voltage (Vth) of a 22nm gate length PMOS device. The gate of the device uses titanium dioxide (TiO2) as the high permittivity material (high-k) layer to replace the traditional silicon dioxide (SiO2) dielectric layer. While the polysilicon (poly-Si) which is also known as self-aligned silicide (SALICIDE) layer, is deposited on top of the high-k dielectric layer and is used to reduce the gate electrode resistance. The virtual fabrication device was designed using the ATHENA and electrical characterization was simulated using ATLAS. These two simulators were combined with the L9 Taguchi's experimental design to aid in the design and optimization of the process parameters for a total of 36 simulation runs. The objective is to minimize the variance in Vth using Taguchi's nominal-the-best signal-to-noise ratio (SNR) analysis. Analysis of the mean (ANOM) was used to determine the best settings for the process parameters while Analysis of variance (ANOVA) was used to reduce the variability of V th. The results show that the Vth values with the least variance is -0.289 V � 12.7% which is well within the prediction by the International Technology Roadmap for Semiconductors (ITRS) 2011. � 2013 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo6706489
dc.identifier.doi10.1109/RSM.2013.6706489
dc.identifier.epage129
dc.identifier.scopus2-s2.0-84893619716
dc.identifier.spage126
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84893619716&doi=10.1109%2fRSM.2013.6706489&partnerID=40&md5=19ac59f58bdd8d8790e56c6fae4abc67
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29435
dc.pagecount3
dc.sourceScopus
dc.sourcetitleProceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics
dc.subject22 nm gate length PMOS
dc.subjecthigh-k/SALICIDE
dc.subjectTaguchi Method
dc.subjectthreshold voltage
dc.subjectOptimization
dc.subjectSignal to noise ratio
dc.subjectSilicides
dc.subjectTaguchi methods
dc.subjectTitanium dioxide
dc.subjectElectrical characterization
dc.subjectGate electrode resistance
dc.subjectGate length
dc.subjectHigh-k dielectric layers
dc.subjecthigh-k/SALICIDE
dc.subjectHigh-permittivity material
dc.subjectInternational Technology Roadmap for Semiconductors
dc.subjectSignaltonoise ratio (SNR)
dc.subjectThreshold voltage
dc.titleThreshold voltage optimization in a 22nm High-k/Salicide PMOS deviceen_US
dc.typeConference paperen_US
dspace.entity.typePublication
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