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Threshold voltage and leakage current variability on process parameter in a 22nm PMOS Device

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dc.citedby2
dc.contributor.authorAfifah Maheran A.H.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorNoor Faizah Z.A.en_US
dc.contributor.authorMohd Zain A.S.en_US
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorSayed N.M.en_US
dc.contributor.authorid36570222300en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid56395444600en_US
dc.contributor.authorid55925762500en_US
dc.contributor.authorid36239165300en_US
dc.contributor.authorid57203514554en_US
dc.date.accessioned2023-05-29T06:56:33Z
dc.date.available2023-05-29T06:56:33Z
dc.date.issued2018
dc.description.abstractThis article explains the effect of variation on the process parameters while designing a Nano-scaled planar PMOS device in complementary metal-oxide-semiconductor (CMOS) technology for 22 nm gate length. This procedure aims to meet the best combination of fabrication process parameter on the threshold voltage (VTH) and leakage current (IOFF) which was predicted by the International Technology Roadmap for Semiconductors (ITRS). The gate structure of the PMOS device consists of Titanium Dioxide (TiO2) as the high permittivity material (high-k) dielectric and Tungsten Silicide (WSix) metal gate where it is deposited on top of the TiO2 high-k layer. The simulation process was designed using an industrial-based numerical simulator. This simulator was then aided in design with the L9 Taguchi�s orthogonal array method to optimise the best combination of process parameters in order to achieve the optimum VTH value with the lowest IOFF. The analysis results of the factor effect on the SNR in ANOVA analysis clearly show that the Halo implantation tilting angle has the greatest influence with 52.47% in optimising the process parameter where the implantation tilting angle is at 35�. The final results in characterizing and modelling the process parameters of the 22 nm PMOS device with reference to the prediction ITRS succeeded where the result of the VTH is 4.25% closest to the prediction value of -0.289 V � 12.7% and minimum IOFF value which is 92% away from the predicted value which is 100 nA/�m. � 2018 Universiti Teknikal Malaysia Melaka. All Rights Reserved.en_US
dc.description.natureFinalen_US
dc.identifier.epage13
dc.identifier.issue2-Aug
dc.identifier.scopus2-s2.0-85052015761
dc.identifier.spage9
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85052015761&partnerID=40&md5=4d68abc065fda152b6404adb69dac63c
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/24184
dc.identifier.volume10
dc.publisherUniversiti Teknikal Malaysia Melakaen_US
dc.sourceScopus
dc.sourcetitleJournal of Telecommunication, Electronic and Computer Engineering
dc.titleThreshold voltage and leakage current variability on process parameter in a 22nm PMOS Deviceen_US
dc.typeArticleen_US
dspace.entity.typePublication
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