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Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method

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dc.citedby2
dc.contributor.authorMaheran A.H.A.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorShaari S.en_US
dc.contributor.authorKalaivani T.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorFaizah Z.A.N.en_US
dc.contributor.authorApte P.R.en_US
dc.contributor.authorid36570222300en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid6603595092en_US
dc.contributor.authorid56989358500en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid56395444600en_US
dc.contributor.authorid55725529100en_US
dc.date.accessioned2023-05-16T02:45:42Z
dc.date.available2023-05-16T02:45:42Z
dc.date.issued2014
dc.description.abstractThis paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (Vth). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO2/Poly-Si technology. For this, Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate. The simulation results show that the optimal threshold voltage (Vth) of -0.289 V ± 12.7% is achieved in accordance to the ITRS 2012 specifications. This provides a benchmark towards the fabrication of 22 nm planar PMOS in future work. © 2014 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo6920825
dc.identifier.doi10.1109/SMELEC.2014.6920825
dc.identifier.epage181
dc.identifier.scopus2-s2.0-84908224581
dc.identifier.spage178
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84908224581&doi=10.1109%2fSMELEC.2014.6920825&partnerID=40&md5=511aa1478155e5ad91939e558888bd29
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/21851
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceScopus
dc.sourcetitleIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
dc.titleEffect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi methoden_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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