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Control factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi method

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dc.citedby4
dc.contributor.authorAfifah Maheran A.H.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorMohd A.S.en_US
dc.contributor.authorNoor Z.A.en_US
dc.contributor.authorElgomati H.A.en_US
dc.contributor.authorid36570222300en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid36239165300en_US
dc.contributor.authorid57196423028en_US
dc.contributor.authorid57196411125en_US
dc.contributor.authorid36536722700en_US
dc.date.accessioned2023-05-29T06:40:09Z
dc.date.available2023-05-29T06:40:09Z
dc.date.issued2017
dc.description.abstractIn this article, Taguchi method was used to optimize the control factor in obtaining the optimal value which is also known as response characteristics, where the threshold voltage (Vth) and leakage current (Ileak) for NMOS transistor with a gate length of 22 nm is taken into account. The NMOS transistor design includes a high permittivity material (high-k) as a dielectric layer and a metal gate which is Titanium Dioxide (TiO2) and Tungsten Silicide (WSiX) respectively. The control factor was optimized in designing the NMOS device using the Taguchi Orthogonal Array Method where the Signal-To-Noise Ratio (SNR) analysis uses the Nominal-The-Best (NTB) SNR for Vth, while for Ileak analysis, a Smaller-The-Better (STB) SNR was used. Four manufacturing control factors and two noise factor are used to optimize the response characteristics and find the best combination of design parameters. The results show that the Halo implantation tilting angle is the dominant factor where it has the greatest factor effect on the SNR of the Ileak with 55.52%. It is also shown that the values of Vth have the least variance and the mean value can be set to 0.289 V � 12.7% and Ileak is less than 100 nA/?m which is in line with the projections made by the International Technology Roadmap for Semiconductors (ITRS).en_US
dc.description.natureFinalen_US
dc.identifier.epage141
dc.identifier.issue2-Jul
dc.identifier.scopus2-s2.0-85032895208
dc.identifier.spage137
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85032895208&partnerID=40&md5=8b6c0a5c34c140a29badb7cd6a3ba0d5
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/23398
dc.identifier.volume9
dc.publisherUniversiti Teknikal Malaysia Melakaen_US
dc.sourceScopus
dc.sourcetitleJournal of Telecommunication, Electronic and Computer Engineering
dc.titleControl factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi methoden_US
dc.typeArticleen_US
dspace.entity.typePublication
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