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Signature verification system : an approach using logic system

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dc.contributor.affiliationen_US
dc.contributor.authorYogesh Verma Krishnanen_US
dc.date.accessioned2023-05-03T15:29:39Z
dc.date.available2023-05-03T15:29:39Z
dc.date.issued2009
dc.description.abstractThis thesis describes the work completed for the final year project, design of a signature verification system.en_US
dc.description.endpage172en_US
dc.description.startpage1en_US
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/20873
dc.language.isoenen_US
dc.titleSignature verification system : an approach using logic systemen_US
dc.typeResource Types::text::Final Year Projecten_US
dspace.entity.typePublication
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