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Process parameters optimization of 14nm p-type MOSFET using 2-D analytical modeling

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dc.citedby1
dc.contributor.authorNoor Faizah Z.A.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorKer P.J.en_US
dc.contributor.authorSiti Munirah Y.en_US
dc.contributor.authorMohd Firdaus R.en_US
dc.contributor.authorMah S.K.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorid56395444600en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid37461740800en_US
dc.contributor.authorid57191675888en_US
dc.contributor.authorid58140788300en_US
dc.contributor.authorid57191706660en_US
dc.contributor.authorid57201289731en_US
dc.date.accessioned2023-05-29T06:13:30Z
dc.date.available2023-05-29T06:13:30Z
dc.date.issued2016
dc.description.abstractSimulations of a computer-generated downscaled device at 14nm gate length of p-type MOSFET is conferred in this paper. The device is scaled down from a 32nm transistor which is from the former research. A combination of insulator-conductor that were used includes a high-k material and a metal gate where in this research, Hafnium Dioxide (HfO2) is used as high-k material and Tungsten Silicide (WSi2) is used as a metal gate. A 14nm p-type transistor was virtually fabricated using ATHENA module and characterized its performance evaluation using ATLAS module in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The scaled down device is then optimized through process parameter variability using Taguchi Method. The objective is to find the best combination of fabrication parameter in order to achieve the targeted value of threshold voltage (VTH) and leakage current (IOFF) that are predicted by International Technology Roadmap for Semiconductors (ITRS) 2013. The results show that the ideal value for VTH and IOFF are 0.248635�12.7% V and 5.26x10-12 A/um respectively and the results were achieved according to the ITRS specification.en_US
dc.description.natureFinalen_US
dc.identifier.epage100
dc.identifier.issue4
dc.identifier.scopus2-s2.0-84992520055
dc.identifier.spage97
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84992520055&partnerID=40&md5=aeb0b422532d530683c57829c3f1785f
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/22934
dc.identifier.volume8
dc.publisherUniversiti Teknikal Malaysia Melakaen_US
dc.sourceScopus
dc.sourcetitleJournal of Telecommunication, Electronic and Computer Engineering
dc.titleProcess parameters optimization of 14nm p-type MOSFET using 2-D analytical modelingen_US
dc.typeArticleen_US
dspace.entity.typePublication
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