Publication: Low complexity multidimensional CDF 5/3 DWT architecture
Date
2014
Authors
Al-Azawi S.
Abbas Y.A.
Jidin R.
Journal Title
Journal ISSN
Volume Title
Publisher
Institute of Electrical and Electronics Engineers Inc.
Abstract
This paper introduces an efficient low complexity multidimensional DWT architecture. The proposed architecture is based on a lifting-scheme for the Cohen-Daubechies-Feauveau (CDF) 5/3 DWT filter. It consists of low complexity identical computation and control units which can be used easily to implement 2-D and 3-D DWT architectures. The synthesis results show that the output latency is 2N+2 clock cycles, with N2+2N+2 clock cycles required for the first level 2-D CDF 5/3 DWT computation. The architecture is parameterized to tackle various images and wordlength sizes. Furthermore, the proposed architecture is implemented using a Virtex 6 Xilinx FPGA platform. The implementation results reveal that the proposed architecture can operate at up to 198 MHz operating frequency. This reduces the time for first level DWT decomposition of a 512×512-pixel image to less than 1.3 m sec. © 2014 IEEE.