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Modelling of process parameters for 32nm PMOS transistor using Taguchi method

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dc.citedby15
dc.contributor.authorElgomati H.A.en_US
dc.contributor.authorMajlis B.Y.en_US
dc.contributor.authorHamid A.M.A.en_US
dc.contributor.authorSusthitha P.M.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorid36536722700en_US
dc.contributor.authorid6603071546en_US
dc.contributor.authorid36570222300en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid12792216600en_US
dc.date.accessioned2023-12-28T06:30:20Z
dc.date.available2023-12-28T06:30:20Z
dc.date.issued2012
dc.description.abstractAs CMOS technology scales down to the nanometer level process variation can produce deviation in device parameters which affect circuit performance. In this paper, we investigate the effect of seven process parameters and two process noise parameters on threshold voltage (Vth) in a 32nm PMOS transistor. Using Taguchi's experimental robust design strategy seven process parameters were assigned to 7 columns of the L18 orthogonal array to conduct 18 simulation runs. Fabrication of the 32nm PMOS transistor was simulated by using the fabrication tool ATHENA and electrical characterization was simulated using ATLAS. These simulators were used for computing Vth simulations for each row of the L18 array with 4 combinations of the 2 noise factors. Taguchi's nominal-the-best S/N ratio was used as the objective functions for the minimization of variance in Vth. The best settings of process parameters were determined using Analysis of Mean (ANOM) and Analysis of Variance (ANOVA) for reducing the variability of Vth. The best settings were used for verification simulations and the results showed that the Vth values had the least variance and the mean value could be adjusted to-0.103V +-0.003 for PMOS, which is well within ITRS specifications. � 2012 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo6243918
dc.identifier.doi10.1109/AMS.2012.22
dc.identifier.epage45
dc.identifier.scopus2-s2.0-84866527184
dc.identifier.spage40
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84866527184&doi=10.1109%2fAMS.2012.22&partnerID=40&md5=1fceca229dcf7ab301bcd180294b3885
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29521
dc.pagecount5
dc.sourceScopus
dc.sourcetitleProceedings - 6th Asia International Conference on Mathematical Modelling and Computer Simulation, AMS 2012
dc.subject32nm PMOS
dc.subjectANOM
dc.subjectANOVA
dc.subjectcompensation implantations
dc.subjectL18 orthogonal array
dc.subjectTaguchi Method
dc.subjectThreshold voltage
dc.subjectAnalysis of variance (ANOVA)
dc.subjectCMOS integrated circuits
dc.subjectComputer simulation
dc.subjectTaguchi methods
dc.subjectThreshold voltage
dc.subject32nm PMOS
dc.subjectAnalysis of means
dc.subjectANOM
dc.subjectCircuit performance
dc.subjectCMOS technology
dc.subjectDevice parameters
dc.subjectElectrical characterization
dc.subjectFabrication tool
dc.subjectL18 orthogonal array
dc.subjectMean values
dc.subjectModelling of process
dc.subjectNanometer level
dc.subjectNoise factor
dc.subjectObjective functions
dc.subjectpMOS transistors
dc.subjectProcess noise
dc.subjectProcess parameters
dc.subjectRobust designs
dc.subjectS/N ratio
dc.subjectTaguchi
dc.subjectMathematical models
dc.titleModelling of process parameters for 32nm PMOS transistor using Taguchi methoden_US
dc.typeConference paperen_US
dspace.entity.typePublication
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