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Optimizing 35nm NMOS devices V TH and I LEAK by controlling active area and halo implantation dosage

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dc.citedby6
dc.contributor.authorElgomati H.A.en_US
dc.contributor.authorMajlis B.Y.en_US
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorZaharim A.en_US
dc.contributor.authorHamid F.A.en_US
dc.contributor.authorid36536722700en_US
dc.contributor.authorid6603071546en_US
dc.contributor.authorid36239165300en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid15119466900en_US
dc.contributor.authorid6603573875en_US
dc.date.accessioned2023-12-28T07:05:42Z
dc.date.available2023-12-28T07:05:42Z
dc.date.issued2011
dc.description.abstractCMOS transistor reaches physical and electrical limitations technology passes through the critical 90 nm gate size. Scaling down linearly to 35nm, the transistor electrical characteristics behave even more unpredictable. This can be seen with leakage current increasing exponentially as the physical size reduced linearly, mainly caused by the short channel effect. As a result, the threshold voltage (V TH) values becoming to low for the transistor to act as a switch. Containing this leakage current under a desired value is crucial for reliable high-speed chip design. Fabricating a 35nm NMOS transistor, ion implantations is one of a main area that determine the amount of the leakage current. A transistor source/drain is created with that implantation. In our experiment, we used arsenic and phosphorus to dope the active area. The initial fabricated NMOS transistor threshold voltage value is way off ITRS predicted value with at around 5V. Sweeping the active area ion implantation dosage and depth would not give us a working transistor as the best V TH obtained is 3.314V, which is still far off the ITRS prediction of 0.12V. As such we also vary the transistor halo ion implantation dosage and power. In theory, halo implantation is supposed to shift the threshold voltage of the transistor and significantly reduce the short channel effect that causes the said leakage current due to dopant channeling through polycrystalline silicon grain boundary. Indium was used as the element for halo implantation with the implanting equipment set to 30 degree tilting and 360 degree rotation around the wafer. Hence, we managed to fabricate a transistor that with a threshold voltage of 0.127V with doping concentration of 8.1210 12 particle per m 2. This shows that the design of halo implantation is the key technology for supressing short channel effect and improving subthreshold-slope, I ON and I OFF, adjusting the V TH. The transistor fabrication process of 35 nm NMOS was simulated by using Silvaco ATHENA module and the resulting electrical characterization was simulated using ATLAS module, Taguchi analysis was applied to our experiment results to minimize the time taken to find the best solution. � 2011 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo6088345
dc.identifier.doi10.1109/RSM.2011.6088345
dc.identifier.epage290
dc.identifier.scopus2-s2.0-83755228642
dc.identifier.spage286
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-83755228642&doi=10.1109%2fRSM.2011.6088345&partnerID=40&md5=f0a92717ddf4406d7bd19298b71f8e4c
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29573
dc.pagecount4
dc.sourceScopus
dc.sourcetitle2011 IEEE Regional Symposium on Micro and Nanoelectronics, RSM 2011 - Programme and Abstracts
dc.subject35nm NMOS
dc.subjecthalo implantation
dc.subjecttaguchi
dc.subjectArsenic
dc.subjectExperiments
dc.subjectGrain boundaries
dc.subjectIon implantation
dc.subjectIons
dc.subjectLeakage currents
dc.subjectMOS devices
dc.subjectPhosphorus
dc.subjectPolycrystalline materials
dc.subjectPolysilicon
dc.subjectSilicon wafers
dc.subjectThreshold voltage
dc.subject35nm NMOS
dc.subjectActive area
dc.subjectCMOS transistors
dc.subjectDoping concentration
dc.subjectElectrical characteristic
dc.subjectElectrical characterization
dc.subjectElectrical limitations
dc.subjectFabrication process
dc.subjecthalo implantation
dc.subjectHalo ion implantation
dc.subjectHigh-speed chips
dc.subjectKey technologies
dc.subjectNMOS devices
dc.subjectNMOS transistors
dc.subjectPoly-crystalline silicon
dc.subjectScaling down
dc.subjectShort-channel effect
dc.subjectSilvaco
dc.subjecttaguchi
dc.subjectTaguchi analysis
dc.subjectTransistors
dc.titleOptimizing 35nm NMOS devices V TH and I LEAK by controlling active area and halo implantation dosageen_US
dc.typeConference paperen_US
dspace.entity.typePublication
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