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Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device

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dc.contributor.authorAtan N.B.en_US
dc.contributor.authorAhmad I.B.en_US
dc.contributor.authorMajlis B.B.Y.en_US
dc.contributor.authorFauzi I.B.A.en_US
dc.contributor.authorid26422792900en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid6603071546en_US
dc.contributor.authorid57204365522en_US
dc.date.accessioned2023-05-29T06:00:28Z
dc.date.available2023-05-29T06:00:28Z
dc.date.issued2015
dc.description.abstractThe process parameters are very crucial factor in the development of transistors. There are many process parameters that influenced in the development of the transistors. In this research, we investigate the effects of the process parameters variation on response characteristics such as threshold voltage (V TH ) and sub-threshold leakage current (I OFF ) in 18nm NMOS device. The technique to identify semiconductor process parameters whose variability would impact most on the device characteristic is realized through the process by using Taguchi robust design method. This paper presents the process parameters that influenced in threshold voltage (V TH ) and sub-threshold leakage current (I OFF ) which includes the Halo Implantation, Compensation Implantation, Adjustment Threshold voltage Implantation and Source/Drain Implantation. The design, fabrication and characterization of 18nm HfO 2 /TiSi 2 NMOS device is simulated and performed via a tool called Virtual Wafer Fabrication (VWF) Silvaco TCAD Tool known as ATHENA and ATLAS simulators. These two simulators were combined with Taguchi L9 Orthogonal method to aid in the design and the optimization of the process parameters to achieve the optimum average of threshold voltage (V TH ) and sub-threshold leakage current, (I OFF ) in 18nm device. Results from this research were obtained; where Halo Implantation dose was identified as one of the process parameter that has the strongest effect on the response characteristics. Whereby the Compensation Implantation dose was identified as an adjustment factor to get the nominal values of threshold voltage V TH , and sub-threshold leakage current, I OFF for 18nm NMOS devices equal to 0.302849 volts and 1.9123�10 -16 A/?m respectively. The design values are referred to ITRS 2011 prediction. � 2015 AIP Publishing LLC.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo110002
dc.identifier.doi10.1063/1.4915221
dc.identifier.scopus2-s2.0-84988273246
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84988273246&doi=10.1063%2f1.4915221&partnerID=40&md5=4d10736ef69ef7fa24a8c11afc1fc64c
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/22361
dc.identifier.volume1657
dc.publisherAmerican Institute of Physics Inc.en_US
dc.sourceScopus
dc.sourcetitleAIP Conference Proceedings
dc.titleInfluence of process parameters on threshold voltage and leakage current in 18nm NMOS deviceen_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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