Publication:
Scaling down of the 32 nm to 22 nm gate length NMOS transistor

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dc.citedby11
dc.contributor.authorAfifah Maheran A.H.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorElgomati H.A.en_US
dc.contributor.authorMajlis B.Y.en_US
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorid36570222300en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid36536722700en_US
dc.contributor.authorid6603071546en_US
dc.contributor.authorid36239165300en_US
dc.date.accessioned2023-12-28T06:30:18Z
dc.date.available2023-12-28T06:30:18Z
dc.date.issued2012
dc.description.abstractIn this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work. � 2012 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo6417117
dc.identifier.doi10.1109/SMElec.2012.6417117
dc.identifier.epage176
dc.identifier.scopus2-s2.0-84874126874
dc.identifier.spage173
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84874126874&doi=10.1109%2fSMElec.2012.6417117&partnerID=40&md5=a8496493fb2de00c10232229a23d44f5
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29515
dc.pagecount3
dc.sourceScopus
dc.sourcetitle2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings
dc.subjecthigh-k/metal gate
dc.subjectScaling down ratio
dc.subjectSilvaco
dc.subjectLeakage currents
dc.subjectSilicides
dc.subjectTungsten
dc.subjectDesign and simulation
dc.subjectDesign simulations
dc.subjectDown-scaling
dc.subjectElectrical characterization
dc.subjectFabrication tool
dc.subjectGate length
dc.subjectMetal gate
dc.subjectNMOS transistors
dc.subjectOptimal values
dc.subjectScale down
dc.subjectScaling down
dc.subjectSilvaco
dc.subjectTiO
dc.subjectTungsten silicide
dc.subjectTitanium dioxide
dc.titleScaling down of the 32 nm to 22 nm gate length NMOS transistoren_US
dc.typeConference paperen_US
dspace.entity.typePublication
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