Publication:
Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method

dc.citedby7
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorHamid F.A.en_US
dc.contributor.authorZaharim A.en_US
dc.contributor.authorid36239165300en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid6603573875en_US
dc.contributor.authorid15119466900en_US
dc.date.accessioned2023-12-28T07:17:54Z
dc.date.available2023-12-28T07:17:54Z
dc.date.issued2010
dc.description.abstractTaguchi method was used to analyze the experimental data in order to get the optimum average of silicide thickness in 45nm devices. The virtually fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were used as design tools and helps to reduce design time and cost. In this paper, both modules and Taguchi method was combined to aid in design and optimizer the process parameters. There are four process parameters (factors), namely Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. These factors were varied for 3 levels to perform 9 experiments. Threshold voltage (VTH) results were used as the evaluation variables. Then, the results were subjected to the Taguchi method for determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were successfully verified with ATHENA and ATLAS's simulator. The results show that the average of silicide thickness after optimizations approaches was 30.66nm and 30.58nm for NMOS and PMOS devices respectively. In this research, Halo Implantation was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as an adjustment factor to get the nominal values of threshold voltage for PMOS and NMOS devices equal to -0.1501V and +0.150047V respectively. � 2010 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo5549488
dc.identifier.doi10.1109/SMELEC.2010.5549488
dc.identifier.epage24
dc.identifier.scopus2-s2.0-77957565255
dc.identifier.spage19
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-77957565255&doi=10.1109%2fSMELEC.2010.5549488&partnerID=40&md5=5ebdbea0ecee161a5c0bb60623509ffc
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29654
dc.pagecount5
dc.sourceScopus
dc.sourcetitleIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
dc.subjectCobalt salicide
dc.subjectOptimizations of 45nm CMOS
dc.subjectSilvaco
dc.subjectTaguchi method
dc.subjectCMOS integrated circuits
dc.subjectCobalt
dc.subjectCobalt compounds
dc.subjectDesign
dc.subjectOptimization
dc.subjectSemiconductor growth
dc.subjectSilicides
dc.subjectTaguchi methods
dc.subjectThreshold voltage
dc.subjectAnneal temperatures
dc.subjectCMOS technology
dc.subjectCobalt salicide
dc.subjectDesign time
dc.subjectDesign tool
dc.subjectElectrical characterization
dc.subjectExperimental data
dc.subjectHalo implantation
dc.subjectNMOS devices
dc.subjectOptimal process
dc.subjectOptimizers
dc.subjectOxide growth
dc.subjectPMOS devices
dc.subjectProcess parameters
dc.subjectResponse characteristic
dc.subjectSilvaco
dc.subjectTaguchi
dc.subjectMOS devices
dc.titleAnalyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi methoden_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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