Publication:
FSM based green memory design and its implementation on ultrascale plus FPGA

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dc.citedby3
dc.contributor.authorPandey B.en_US
dc.contributor.authorMohamed R.R.en_US
dc.contributor.authorTomar G.S.en_US
dc.contributor.authorHussain D.M.A.en_US
dc.contributor.authorBaker El-Biary Y.A.en_US
dc.contributor.authorid57203239026en_US
dc.contributor.authorid56996859800en_US
dc.contributor.authorid16176798100en_US
dc.contributor.authorid8645638300en_US
dc.contributor.authorid57195625873en_US
dc.date.accessioned2023-05-29T08:12:44Z
dc.date.available2023-05-29T08:12:44Z
dc.date.issued2020
dc.description.abstractIn this work, we are going to design a memory using Verilog programming in Vivado 2018.3 Integrated Development Environment and implement it on Kintex UltraScale+ FPGA. In order to make it green, we are reducing power dissipation of our design using power supply settings of UltraScale FPGA that support a dual-voltage operation of the primary core fabric. Operating Voltage (VCCINT) of 7 Series (28nm) VNOM, UltraScale (20nm) VNOM, UltraScale+ (16nm) VNOM, and UltraScale+ (16nm) VLOW are 1V, 0.95V, 0.85V, and 0.72V respectively. In our work, we are 0.873 V operating voltage and compare its power dissipation with power dissipation by 0.9V and 0.928 V operating voltage. There is 2.87-6.42 % reduction in power dissipation when we scale down supply voltage from 0.928 V to 0.873 V. � 2020 Innovare Academics Sciences Pvt. Ltd. All rights reserved.en_US
dc.description.natureFinalen_US
dc.identifier.doi10.31838/jcr.07.19.59
dc.identifier.epage458
dc.identifier.issue19
dc.identifier.scopus2-s2.0-85090123365
dc.identifier.spage454
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85090123365&doi=10.31838%2fjcr.07.19.59&partnerID=40&md5=fc7e99f9984707cb70f88abe3debf956
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/25685
dc.identifier.volume7
dc.publisherInnovare Academics Sciences Pvt. Ltden_US
dc.sourceScopus
dc.sourcetitleJournal of Critical Reviews
dc.titleFSM based green memory design and its implementation on ultrascale plus FPGAen_US
dc.typeArticleen_US
dspace.entity.typePublication
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