Publication:
Improved series resistance model for CMOS ESD diodes

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dc.citedby1
dc.contributor.authorKamal N.B.en_US
dc.contributor.authorKordesch A.V.en_US
dc.contributor.authorAhmad I.B.en_US
dc.contributor.authorid26633062900en_US
dc.contributor.authorid22934876900en_US
dc.contributor.authorid12792216600en_US
dc.date.accessioned2023-12-29T07:57:33Z
dc.date.available2023-12-29T07:57:33Z
dc.date.issued2008
dc.description.abstractCompact diode models normally available in commercial simulators like Spectre or HSPICE do not scale the series resistance with P-N distance. The standard diode models scale with drawn area, assuming the current is vertical. However the diodes used for ESD protection in CMOS are operating as lateral diodes, so the resistance should scale with width, not area. This is a serious problem for circuit designers. Accurate series resistance in the diode forward region is critical especially for designing ESD protection circuits. This paper analyzes the effect of diode width and P to N (P active to N-tap active) distance on the extracted model Rs value in the standard level 3 SPICE diode model. Diodes of various widths and P-N distance were designed and fabricated in a CMOS 130 nm technology to get actual data measurements. Parameter extraction was done using the commercial BSIMProPlus model extraction software. Different diode widths and P-N distances produce forward IV curves with different slope, due to the changing series resistance. The slope represents the incremental series resistance. This study has been done with two types of diode, PN diode (P active in Nwell diode) and NP diode (N active in Pwell diode). The extracted Rs value shows a linear relationship to P-N distance and is proportional to inverse drawn width. � 2008 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo4770369
dc.identifier.doi10.1109/SMELEC.2008.4770369
dc.identifier.epage486
dc.identifier.scopus2-s2.0-65949111077
dc.identifier.spage484
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-65949111077&doi=10.1109%2fSMELEC.2008.4770369&partnerID=40&md5=50b5a7c1884b595a29637ce3e6ac5249
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/30997
dc.pagecount2
dc.sourceScopus
dc.sourcetitleIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
dc.subjectElectrostatic devices
dc.subjectElectrostatic discharge
dc.subjectParameter extraction
dc.subjectSemiconductor diodes
dc.subjectSimulators
dc.subjectCircuit designers
dc.subjectCommercial simulators
dc.subjectData measurements
dc.subjectDifferent slopes
dc.subjectESD protection
dc.subjectESD protection circuit
dc.subjectI - V curve
dc.subjectLinear relationships
dc.subjectModel extraction
dc.subjectP-n Diode
dc.subjectSeries resistances
dc.subjectDiodes
dc.titleImproved series resistance model for CMOS ESD diodesen_US
dc.typeConference paperen_US
dspace.entity.typePublication
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