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LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage

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dc.citedby1
dc.contributor.authorIslam S.Z.en_US
dc.contributor.authorAli M.A.M.en_US
dc.contributor.authorid55432804400en_US
dc.contributor.authorid6507416666en_US
dc.date.accessioned2023-12-29T07:56:16Z
dc.date.available2023-12-29T07:56:16Z
dc.date.issued2008
dc.description.abstractThis paper presents a low hardware overhead scan- based test pattern generator (TPG) that can reduce switching activity in circuit under test (CUT) during test and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed TPG is comprised of two TPGs: Seed selected Random Test Pattern Generator (RTPG) and 3-weight Weighted Random Built-in-Self Test (WRBIST). Test pattern generated by seed selected RTPG detect easy-to-detect faults and test pattern generated by 3-weight WRBIST detect hard faults that remain undetected after seed selected RTPG patterns are applied. Experimental results show that the proposed TPG schemes can attain 100% fault coverage for all benchmark circuits with drastically reduced test sequence lengths. This reduction in test sequence length achieved at low hardware cost even for benchmark circuits that have large number of scan inputs. � 2008 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo4746380
dc.identifier.doi10.1109/APCCAS.2008.4746380
dc.identifier.epage1758
dc.identifier.scopus2-s2.0-62949244911
dc.identifier.spage1755
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-62949244911&doi=10.1109%2fAPCCAS.2008.4746380&partnerID=40&md5=5485713f9b62bea77c40fdb2e1c5119b
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/30942
dc.pagecount3
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceScopus
dc.sourcetitleIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
dc.subjectCost reduction
dc.subjectHardware
dc.subjectBenchmark circuit
dc.subjectCircuit under test
dc.subjectFault coverages
dc.subjectHardware overheads
dc.subjectHybrid patterns
dc.subjectLow hardware costs
dc.subjectLow-power dissipation
dc.subjectSwitching activities
dc.subjectBuilt-in self test
dc.titleLFSR based hybrid pattern scheme achieving low power dissipation and high fault coverageen_US
dc.typeConference paperen_US
dspace.entity.typePublication
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