Publication:
High performance FPGA architecture for dual mode processor of Integer Haar Lifting-based Wavelet Transform

Simple item page
dc.citedby7
dc.contributor.authorShahadi H.I.en_US
dc.contributor.authorJidin R.en_US
dc.contributor.authorWay W.H.en_US
dc.contributor.authorid54956597100en_US
dc.contributor.authorid6508169028en_US
dc.contributor.authorid55936039400en_US
dc.date.accessioned2023-12-28T04:12:54Z
dc.date.available2023-12-28T04:12:54Z
dc.date.issued2013
dc.description.abstractDiscrete Wavelet Transform (DWT) becomes a major part for many applications. Fast, low area, and low power consumption hardware for DWT is necessary for some new technologies such as OFDM transceiver and wireless multimedia sensor networks. This paper presents efficient dual mode (decomposition and reconstruction) Integer Haar Lifting Wavelet Transform (IHLWT) architecture. The proposed architecture reduces the hardware requirements by exploiting the arithmetic operations redundancy which is involved in IHLWT computations. It is multiplier-free and it performs IHLWT with only a single adder and subtractor which have reconfigurable input buses to perform decomposition and reconstruction transformations. IEEE standard VHDL has been used to develop the proposed processor. This makes the design vendor independent and therefore easily portable across FPGA devices from multiple vendors. The generic design is flexible and can perform any arbitrary signal length. The synthesis of the processor showed that it requires low number of CLB-slices and low power consumption with high operating-frequency for various Xilinx FPGA devices. The processor has been successfully implemented and tested on Xilinx Spartan6-SP601 Evaluation Board. The implemented hardware has been tested in real time by using many recording audio signals. All the implemented hardware results were identical 100% with IHLWT software results. � 2013 Praise Worthy Prize S.r.l. - All rights reserved.en_US
dc.description.natureFinalen_US
dc.identifier.epage2067
dc.identifier.issue9
dc.identifier.scopus2-s2.0-84888095195
dc.identifier.spage2058
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84888095195&partnerID=40&md5=7570751ae73733f7813ebfee5f1e406f
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29400
dc.identifier.volume8
dc.pagecount9
dc.sourceScopus
dc.sourcetitleInternational Review on Computers and Software
dc.subjectDual mode processor
dc.subjectField programmable gate array (FPGA)
dc.subjectHaar filter
dc.subjectInteger to integer (Int2Int) Wavelet
dc.subjectLifting wavelet transform (LWT)
dc.titleHigh performance FPGA architecture for dual mode processor of Integer Haar Lifting-based Wavelet Transformen_US
dc.typeArticleen_US
dspace.entity.typePublication
Files
Collections
SCOPUS