Publication:
PRINCE IP-core on Field Programmable Gate Arrays (FPGA)

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dc.citedby8
dc.contributor.authorAbbas Y.A.en_US
dc.contributor.authorJidin R.en_US
dc.contributor.authorJamil N.en_US
dc.contributor.authorZ'aba M.R.en_US
dc.contributor.authorRusli M.E.en_US
dc.contributor.authorid56417806700en_US
dc.contributor.authorid6508169028en_US
dc.contributor.authorid36682671900en_US
dc.contributor.authorid24726154700en_US
dc.contributor.authorid16246214600en_US
dc.date.accessioned2023-05-29T06:01:44Z
dc.date.available2023-05-29T06:01:44Z
dc.date.issued2015
dc.description.abstractThis study presents a high execution-speed and low-resource hardware IP-Core of PRINCE light weight block cipher on a Field Programmable Gate Arrays (FPGA). The new FPGA IP-core is to speed-up the performance of PRINCE, superseding software implementation that is typically slow and inefficient. The design of this IP core is based on concurrent concept in encrypting blocks of 64 bits data, in that each block is executed within one clock cycle, resulting in high throughput and low latency. Though this IP core encrypts data at high speed processing, it consumes relatively low power. The hardware design can allow encryption, decryption and key schedule to utilize identical hardware components, in order to reduce further the FPGA resources. This efficient PRINCE hardware architecture has been coded using Very High speed integrated circuit Hardware Description Language (VHDL). Also, a bus interface has been included as part of PRINCE IP core to allow it to communicate with an on-chip microprocessor. The IP core has been successfully synthesized, mapped, simulated and tested on an FPGA evaluation board. The test program that has been written in "C" to evaluate this IP-Core on a Virtex-403 FPGA board yields an encryption throughput of 2.03 Gbps or resource efficiency of 2.126 Mbps/slice. � Maxwell Scientific Organization, 2015.en_US
dc.description.natureFinalen_US
dc.identifier.doi10.19026/rjaset.10.2447
dc.identifier.epage922
dc.identifier.issue8
dc.identifier.scopus2-s2.0-84939240869
dc.identifier.spage914
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84939240869&doi=10.19026%2frjaset.10.2447&partnerID=40&md5=e576191c40ead72bcbf215efcc734b1a
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/22534
dc.identifier.volume10
dc.publisherMaxwell Science Publicationsen_US
dc.relation.ispartofAll Open Access, Gold, Green
dc.sourceScopus
dc.sourcetitleResearch Journal of Applied Sciences, Engineering and Technology
dc.titlePRINCE IP-core on Field Programmable Gate Arrays (FPGA)en_US
dc.typeArticleen_US
dspace.entity.typePublication
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