Publication:
Modeling of 14 nm gate length n-Type MOSFET

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dc.citedby12
dc.contributor.authorFaizah Z.A.N.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorKer P.J.en_US
dc.contributor.authorRoslan P.S.A.en_US
dc.contributor.authorMaheran A.H.A.en_US
dc.contributor.authorid56395444600en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid37461740800en_US
dc.contributor.authorid57188858559en_US
dc.contributor.authorid36570222300en_US
dc.date.accessioned2023-05-29T05:59:36Z
dc.date.available2023-05-29T05:59:36Z
dc.date.issued2015
dc.descriptionDielectric materials; Fabrication; Field effect transistors; Gate dielectrics; Gates (transistor); Hafnium oxides; High-k dielectric; Metals; MOS devices; Nanoelectronics; Oxide semiconductors; Reconfigurable hardware; Threshold voltage; Transistors; ATHENA; ATLAS; High-k/metal gates; Metal gate transistors; MOS-FET; Short-channel effect; Virtual fabrication; Wafer fabrications; MOSFET devicesen_US
dc.description.abstractMetal-Oxide-Semiconductor Field Effect Transistors MOSFETs (MOSFETs) transistor have been scaled tremendously through Moore's Law since 1974 in order to compact transistors in a single chip. Thus, a proper scaling technique is compulsory to minimize the short channel effect (SCE) problems. In this paper, the virtual fabricated design and device's characterization of 14 nm HfO2/WSi2 n-type MOSFET device is presented. The device is scaled based on previous research on 32 nm transistors. The virtual fabrication and simulation of n-type MOSFETs are implemented using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools named ATHENA and ATLAS. From the simulation, result shows that the optimal value of threshold voltage (VTH), drive current (ION) and leakage current (IOFF) are 0.232291 V, 78.922�10-6 A/um and 77.11�10-9 A/um respectively. These simulation results are believed to be able to create a touchstone towards the optimization and fabrication of 14 nm device's gate length utilizing High-K/Metal Gate n-type MOSFET in impending work. � 2015 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo7354988
dc.identifier.doi10.1109/RSM.2015.7354988
dc.identifier.scopus2-s2.0-84963857388
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84963857388&doi=10.1109%2fRSM.2015.7354988&partnerID=40&md5=505b9508ebe838ef68f0c6c30814deb5
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/22203
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceScopus
dc.sourcetitleRSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings
dc.titleModeling of 14 nm gate length n-Type MOSFETen_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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