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Designing and optimizing digital circuit using FPSGA and DH

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dc.citedby0
dc.contributor.authorKamil K.en_US
dc.contributor.authorChong K.H.en_US
dc.contributor.authorRaveendran S.K.en_US
dc.contributor.authorid57195622807en_US
dc.contributor.authorid36994481200en_US
dc.contributor.authorid57064141200en_US
dc.date.accessioned2023-12-28T04:12:49Z
dc.date.available2023-12-28T04:12:49Z
dc.date.issued2013
dc.description.abstractThis paper is presents the analysis of designing and optimizing digital circuit structure using Finite Persisting Sphere Genetic Algorithm (FPSGA) and (Double Helix) DH representation. The design is involved 4 Input and 1 Output of digital circuit with 6 min terms. The resulted circuit is verified using XILINX ISE Design Suite 13.2. The result obtained shows that the circuit is function and able to operate with minimum number of gates. � 2013 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo6564536
dc.identifier.doi10.1109/PEOCO.2013.6564536
dc.identifier.epage171
dc.identifier.scopus2-s2.0-84882767954
dc.identifier.spage167
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84882767954&doi=10.1109%2fPEOCO.2013.6564536&partnerID=40&md5=73eeb53f7826e64909639b80ac567b04
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29383
dc.pagecount4
dc.sourceScopus
dc.sourcetitleProceedings of the 2013 IEEE 7th International Power Engineering and Optimization Conference, PEOCO 2013
dc.subjectEngineering
dc.subjectIndustrial engineering
dc.subjectCircuit structures
dc.subjectDouble helix
dc.subjectNumber of gates
dc.subjectOptimization
dc.titleDesigning and optimizing digital circuit using FPSGA and DHen_US
dc.typeConference paperen_US
dspace.entity.typePublication
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