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Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling

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dc.citedby1
dc.contributor.authorNoor Faizah Z.A.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorKer P.J.en_US
dc.contributor.authorSiti Munirah Y.en_US
dc.contributor.authorMohd Firdaus R.en_US
dc.contributor.authorMd Fazle E.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorid56395444600en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid37461740800en_US
dc.contributor.authorid57191675888en_US
dc.contributor.authorid58140788300en_US
dc.contributor.authorid57191665557en_US
dc.contributor.authorid57201289731en_US
dc.date.accessioned2023-05-29T06:11:25Z
dc.date.available2023-05-29T06:11:25Z
dc.date.issued2016
dc.descriptionHafnium oxides; High-k dielectric; Manufacture; Silicides; Taguchi methods; CMOS transistors; HIGH-K metal gates; Modeling and optimization; Process parameters; Process parameters optimizations; Titanium silicide; Tungsten silicide; Wafer fabrications; Reconfigurable hardwareen_US
dc.description.abstractThis paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively. � 2016 The Authors, published by EDP Sciences.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo1017
dc.identifier.doi10.1051/matecconf/20167801017
dc.identifier.scopus2-s2.0-84992437009
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84992437009&doi=10.1051%2fmatecconf%2f20167801017&partnerID=40&md5=76523956eec5c8c7705426a6d949e14b
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/22635
dc.identifier.volume78
dc.publisherEDP Sciencesen_US
dc.relation.ispartofAll Open Access, Gold, Green
dc.sourceScopus
dc.sourcetitleMATEC Web of Conferences
dc.titleProcess Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modellingen_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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