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Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method

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dc.citedby8
dc.contributor.authorAfifah Maheran A.H.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorShaari S.en_US
dc.contributor.authorid36570222300en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid6603595092en_US
dc.date.accessioned2023-05-16T02:46:53Z
dc.date.available2023-05-16T02:46:53Z
dc.date.issued2014
dc.description.abstractIn this article, Taguchi orthogonal array method was used to optimize the process parameters during the design of a 22 nm n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in order to decrease the leakage current (ILEAK) of the device. Titanium dioxide (TiO2) was used as the dielectric layer to replace the traditional silicon dioxide SiO2 and tungsten silicide (WSix) was used as a metal gate to replace polysilicon. The device's fabrication and electrical characterization were executed using ATHENA and ATLAS modules from Silvaco International. Taguchi's Power of Three Series L9 orthogonal array was used to optimize the device process parameters and to finally predict the best process parameter combination to obtain the minimum leakage current (ILEAK) using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The optimization resulted in the attainment of the lowest ILEAK mean value of 0.25759 nA/?m which is in accordance to the predicted value given in the International Technology Roadmap for Semiconductors (ITRS) 2011. © 2014 Penerbit UTM Press. All rights reserved.en_US
dc.description.natureFinalen_US
dc.identifier.doi10.11113/jt.v68.2994
dc.identifier.epage49
dc.identifier.issue4
dc.identifier.scopus2-s2.0-84906851620
dc.identifier.spage45
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84906851620&doi=10.11113%2fjt.v68.2994&partnerID=40&md5=c478b26ca5525c1c47e71f78d3031c03
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/22042
dc.identifier.volume68
dc.publisherPenerbit UTM Pressen_US
dc.relation.ispartofAll Open Access, Bronze
dc.sourceScopus
dc.sourcetitleJurnal Teknologi (Sciences and Engineering)
dc.titleOptimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi methoden_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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