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Analysis on optimizing the design of low power dynamic latch comparators

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dc.contributor.authorMarufuzzaman M.en_US
dc.contributor.authorRahman L.F.en_US
dc.contributor.authorMutalib N.en_US
dc.contributor.authorSidek L.M.en_US
dc.contributor.authorAlam L.en_US
dc.contributor.authorid57205234835en_US
dc.contributor.authorid36984229900en_US
dc.contributor.authorid57200698010en_US
dc.contributor.authorid35070506500en_US
dc.contributor.authorid37053462100en_US
dc.date.accessioned2023-05-29T08:07:36Z
dc.date.available2023-05-29T08:07:36Z
dc.date.issued2020
dc.description.abstractComparator is a key component in energy-efficient applications such as memory-sensing, radiofrequency identification (RFID), analog-to-digital converter (ADC), etc. Among different types of comparator circuits, the preamplifier-based design is lack of increasing the power consumption due to large current. Moreover, dynamic latch comparators can provide high speed, low offset and high resolution, which makes it highly in demand compared to other comparators schemes. Additionally, the circuit can reduce the power dissipation due to its simple latch circuitry. Therefore, the design optimization of the comparator is a key research area in energy efficiency. Among various comparator circuit existed, the Dynamic Latch Comparators (DLCs) are more power efficient as it removes the usage of preamplifiers. Another important feature in optimizing the DLC circuit is the circuit complexity, rapidity, resolution and low-offset voltage. A very efficient and robust comparator design lead the researchers to analyze various parameters such as propagation delay, technology, power consumption, speed and offset for different types of the comparator. This review paper presents the comparative study between several types of DLCs and the methodologies used in designing optimized latch comparators. Major parameters such as low power and low supply voltages, propagation delay, input offset voltages as well as the techniques are compared among various recently published research works. The results and discussion among the comparison results will act as a design optimization guideline for future researchers especially in the optimization of DLCs. � 2020 Alpha Publishers. All rights reserved.en_US
dc.description.natureFinalen_US
dc.identifier.epage5645
dc.identifier.issue9
dc.identifier.scopus2-s2.0-85094171550
dc.identifier.spage5627
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85094171550&partnerID=40&md5=76ce056e8ddf2860b26941268a1804ca
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/25253
dc.identifier.volume10
dc.publisherAlpha Publishersen_US
dc.sourceScopus
dc.sourcetitleJournal of Green Engineering
dc.titleAnalysis on optimizing the design of low power dynamic latch comparatorsen_US
dc.typeArticleen_US
dspace.entity.typePublication
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