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Design topologies of a cmos charge pump circuit for low power applications

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dc.citedby6
dc.contributor.authorRahman L.F.en_US
dc.contributor.authorMarufuzzaman M.en_US
dc.contributor.authorAlam L.en_US
dc.contributor.authorMokhtar M.B.en_US
dc.contributor.authorid36984229900en_US
dc.contributor.authorid57205234835en_US
dc.contributor.authorid37053462100en_US
dc.contributor.authorid35318290800en_US
dc.date.accessioned2023-05-29T09:08:50Z
dc.date.available2023-05-29T09:08:50Z
dc.date.issued2021
dc.description.abstractApplications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC�DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the charge pump topologies based on input/output voltage, pumping effi-ciency, power dissipation, charge transfer capability, design complexity, pumping capacitor, clock frequencies with a minimum load balance, etc. Finally, this review study summarizes with the discussion on the outline of appropriate schemes and recommendations to future researchers in selecting the most suitable CP design methods for low power applications. � 2021 by the authors. Licensee MDPI, Basel, Switzerland.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo676
dc.identifier.doi10.3390/electronics10060676
dc.identifier.epage13
dc.identifier.issue6
dc.identifier.scopus2-s2.0-85102388169
dc.identifier.spage1
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85102388169&doi=10.3390%2felectronics10060676&partnerID=40&md5=58633fed24597a0412ba62320656e8f1
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/26298
dc.identifier.volume10
dc.publisherMDPI AGen_US
dc.relation.ispartofAll Open Access, Gold
dc.sourceScopus
dc.sourcetitleElectronics (Switzerland)
dc.titleDesign topologies of a cmos charge pump circuit for low power applicationsen_US
dc.typeReviewen_US
dspace.entity.typePublication
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