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Design of a reconfigurable computing platform

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dc.citedby3
dc.contributor.authorPapu J.J.en_US
dc.contributor.authorSee O.H.en_US
dc.contributor.authorid35119451300en_US
dc.contributor.authorid16023044400en_US
dc.date.accessioned2023-12-29T07:53:12Z
dc.date.available2023-12-29T07:53:12Z
dc.date.issued2009
dc.description.abstractThis paper describes a design of a reconfigurable computing platform (RCP) based on the Intel Xeon general purpose processor and the Nallatech BenNUEY-PCI-4E field programmable gate array (FPGA) motherboard. The RCP is built to allow users with little or no knowledge of hardware design to program high performance computing applications that utilizes FPGA as the coprocessor. The RCP utilizes Impulse CoDeveloper which is an electronic system level (ESL) design tool that compiles sequential applications/algorithms in C to synthesizable HDL. A customized platform support package (PSP) was developed within the Impulse CoDeveloper environment to enable the Impulse tools to automatically generate the HDL files and C source codes with supported hardware and software interfaces that is targeted for the RCP. The PSP also automates the synthesis and implementation process integration to generate the bitstream file from the Xilinx ISE foundation tool. Finally, the RCP is made accessible within a LAN with the FUSE TCP/IP Server tool. � 2009 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo5224224
dc.identifier.doi10.1109/CITISIA.2009.5224224
dc.identifier.epage153
dc.identifier.scopus2-s2.0-70449110234
dc.identifier.spage148
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-70449110234&doi=10.1109%2fCITISIA.2009.5224224&partnerID=40&md5=c362dafdfe1f7e01e570f3a277281668
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/30783
dc.pagecount5
dc.sourceScopus
dc.sourcetitle2009 Innovative Technologies in Intelligent Systems and Industrial Applications, CITISIA 2009
dc.subjectComputer hardware
dc.subjectComputer science
dc.subjectDesign
dc.subjectField programmable gate arrays (FPGA)
dc.subjectIndustrial applications
dc.subjectIntegrated circuits
dc.subjectIntelligent systems
dc.subjectLithography
dc.subjectLuminous paint
dc.subjectBit stream
dc.subjectCo-processors
dc.subjectE-field
dc.subjectElectronic system level design
dc.subjectGeneral purpose processors
dc.subjectHardware and software
dc.subjectHardware design
dc.subjectHigh-performance computing applications
dc.subjectImplementation process
dc.subjectNallatech
dc.subjectProgrammable gate array
dc.subjectReconfigurable computing
dc.subjectSource codes
dc.subjectComputer hardware description languages
dc.titleDesign of a reconfigurable computing platformen_US
dc.typeConference paperen_US
dspace.entity.typePublication
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