Publication:
Impact of strained channel on electrical properties of Junctionless Double Gate MOSFET

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dc.citedby1
dc.contributor.authorKaharudin K.E.en_US
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorZain A.S.M.en_US
dc.contributor.authorRoslan A.F.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorid56472706900en_US
dc.contributor.authorid36239165300en_US
dc.contributor.authorid55925762500en_US
dc.contributor.authorid57203514087en_US
dc.contributor.authorid12792216600en_US
dc.date.accessioned2023-05-29T08:09:14Z
dc.date.available2023-05-29T08:09:14Z
dc.date.issued2020
dc.descriptionBand structure; Capacitance; Drain current; Electric field effects; Metals; MOS devices; Oxide semiconductors; Transconductance; Comparative analysis; Comprehensive analysis; Double gate MOSFET; Dynamic power dissipation; Intrinsic gate capacitance; Intrinsic gate delay; Strained channels; Transconductance generation factors; Power MOSFETen_US
dc.description.abstractApplication of strained channel in Metal-oxide-semiconductor Field Effect Transistors (MOSFET) technology influences the electrical properties due to the significant changes in the energy band structure of silicon lattices. Thus, in this paper, a comprehensive analysis is conducted to investigate the impact of strained channel towards several electrical properties of junctionless double-gate MOSFET. The comparative analysis is carried out by simulating two different sets of device structure which are JLDGM device (without strain) and junctionless double-gate strained MOSFET (JLDGSM) device. The results show that the strained channel has improved the on-state current (ION), on-off ratio, transconductance (gm) and transconductance generation factor (TGF) by approximately 58 %, 98%, 98%, and 44% respectively. The significant improvement is mainly attributed to the presence of biaxial strain boosting the electron mobility in the channel. The intrinsic gate delay (?int) has significantly reduced by approximately 52% as the strained channel is applied. Since the variation of intrinsic gate capacitances (Cint) is very minimal (4%) as the strained channel is applied, the gate delay is dominantly governed by the drain current. However, the application of strain channel has increased the dynamic power dissipation (Pdyn) for approximately 19% mainly due to slightly increased intrinsic gate capacitances. � 2020 IOP Publishing Ltd. All rights reserved.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo12045
dc.identifier.doi10.1088/1742-6596/1502/1/012045
dc.identifier.issue1
dc.identifier.scopus2-s2.0-85087105182
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85087105182&doi=10.1088%2f1742-6596%2f1502%2f1%2f012045&partnerID=40&md5=712e7274d5697c6c3b7829d2d9e772dc
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/25423
dc.identifier.volume1502
dc.publisherInstitute of Physics Publishingen_US
dc.relation.ispartofAll Open Access, Gold
dc.sourceScopus
dc.sourcetitleJournal of Physics: Conference Series
dc.titleImpact of strained channel on electrical properties of Junctionless Double Gate MOSFETen_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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