Publication:
Characterization of fabrication process noises for 32nm NMOS devices

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dc.citedby0
dc.contributor.authorElgomati H.A.en_US
dc.contributor.authorMajlis B.Y.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorZiad T.en_US
dc.contributor.authorid36536722700en_US
dc.contributor.authorid6603071546en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid36538607500en_US
dc.date.accessioned2023-12-29T07:50:29Z
dc.date.available2023-12-29T07:50:29Z
dc.date.issued2010
dc.description.abstractThis paper describes the effect of fabrication process noises to Sub-nanometer devices, which in this case a 32nm NMOS transistor. This experiment a part of a full Taguchi Method analysis to obtain an optimum fabrication recipe for the said transistor. The two noises introduced in the fabrication is �1�C variation in sacrificial oxide layer growth by diffusion temperature and also silicide compress annealing temperature. In this project, a working 32 NMOS transistor fabrication is used. By increasing the sacrificial oxide layer diffusion temperature from 900�C to 901�C, the reference 32nm NMOS transistor threshold voltage (VTH) jumps from 0.1181V to 0.1394V, while leakage current drops from 0.111mA/um to 0.109 mA/um. By decreasing the silicide compress temperature from 910�C to 909�C, threshold voltage increase slightly from 0.118053V to 0.118068V, This shows a very different in magnitude of effect from same degree of noise introduce to the fabrication process. � 2010 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo5549581
dc.identifier.doi10.1109/SMELEC.2010.5549581
dc.identifier.epage255
dc.identifier.scopus2-s2.0-77957602886
dc.identifier.spage252
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-77957602886&doi=10.1109%2fSMELEC.2010.5549581&partnerID=40&md5=e340f7f826382926c67bac76123e58b5
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/30628
dc.pagecount3
dc.sourceScopus
dc.sourcetitleIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
dc.subjectFabrication
dc.subjectMOS devices
dc.subjectSemiconductor growth
dc.subjectSilicides
dc.subjectTaguchi methods
dc.subjectThreshold voltage
dc.subjectAnnealing temperatures
dc.subjectDegree of noise
dc.subjectDiffusion temperature
dc.subjectFabrication process
dc.subjectNanometer device
dc.subjectNMOS devices
dc.subjectNMOS transistors
dc.subjectOptimum fabrication
dc.subjectSacrificial oxide
dc.subjectTransistors
dc.titleCharacterization of fabrication process noises for 32nm NMOS devicesen_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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