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Photon: A new mix columns architecture on FPGA

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dc.contributor.authorAbbas Y.A.en_US
dc.contributor.authorJidin R.en_US
dc.contributor.authorJamil N.en_US
dc.contributor.authorZ'aba M.R.en_US
dc.contributor.authorMohamed M.A.en_US
dc.contributor.authorid56417806700en_US
dc.contributor.authorid6508169028en_US
dc.contributor.authorid36682671900en_US
dc.contributor.authorid24726154700en_US
dc.contributor.authorid57194596063en_US
dc.date.accessioned2023-05-29T06:53:23Z
dc.date.available2023-05-29T06:53:23Z
dc.date.issued2018
dc.description.abstractLightweight cryptography is an important element in smart devices that require data security as one of the features. These smart devices utilize cryptography when transferring sensitive data. Most of the smart devices are resource constrained devices and thus possess limited computing capability and low memory space. The PHOTON hash function algorithm is a promising lightweight cryptography approach for resource-constrained devices. It has a complex operation called MixColumns. This paper presents a new MixColumns architecture for PHOTON implemented on Field Programmable Gate Array (FPGA) device. In our design, the number of complex multiplication opera-tions is reduced by utilizing comparators that are based on four-bit Galois operations. The efficient PHOTON hardware design was coded using a very high speed integrated circuit hardware description language, VHDL. The design was successfully synthesized, mapped, simu-lated and tested on two FPGA evaluation boards namely, Sparten3 and Artix-7. The results show that the proposed design achieve a throughput of 582 Mbps and an efficiency of 1.55 Gbps/slice for Spartan3, while a throughput of 1.41 Gbps and efficiency of 8.66 Gbps/slice are obtained for Artix-7. The performance on both platforms has superseded performance of existing implementations in litera-ture. � 2018 Yasir Amer Abbas et. al.en_US
dc.description.natureFinalen_US
dc.identifier.epage144
dc.identifier.issue2.14 Special Issue 14
dc.identifier.scopus2-s2.0-85082368223
dc.identifier.spage138
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85082368223&partnerID=40&md5=fd0444dcb3e36317f218200f5c317ae8
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/23946
dc.identifier.volume7
dc.publisherScience Publishing Corporation Incen_US
dc.sourceScopus
dc.sourcetitleInternational Journal of Engineering and Technology(UAE)
dc.titlePhoton: A new mix columns architecture on FPGAen_US
dc.typeArticleen_US
dspace.entity.typePublication
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