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Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor

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dc.citedby22
dc.contributor.authorAfifah Maheran A.H.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorShaari S.en_US
dc.contributor.authorElgomati H.A.en_US
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorid36570222300en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid6603595092en_US
dc.contributor.authorid36536722700en_US
dc.contributor.authorid36239165300en_US
dc.date.accessioned2023-12-28T04:13:13Z
dc.date.available2023-12-28T04:13:13Z
dc.date.issued2013
dc.description.abstractIn this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO2), while the metal gate is Tungsten Silicide (WSix). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (Vth). The objective of this experiment is to minimize the variance of Vth where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of Vth. The results show that the Vth values have least variance and the mean value can be adjusted to 0.306V �0.027 for the NMOS device which is in line with projections by the ITRS specifications.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo12026
dc.identifier.doi10.1088/1742-6596/431/1/012026
dc.identifier.issue1
dc.identifier.scopus2-s2.0-84876950567
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84876950567&doi=10.1088%2f1742-6596%2f431%2f1%2f012026&partnerID=40&md5=315facb720a627ed87e9be4430271e60
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29461
dc.identifier.volume431
dc.publisherInstitute of Physics Publishingen_US
dc.relation.ispartofAll Open Access; Bronze Open Access
dc.sourceScopus
dc.sourcetitleJournal of Physics: Conference Series
dc.subjectMetal analysis
dc.subjectNanotechnology
dc.subjectSignal to noise ratio
dc.subjectSilicides
dc.subjectTaguchi methods
dc.subjectThreshold voltage
dc.subjectTitanium dioxide
dc.subjectAnalysis of means
dc.subjectDesign and optimization
dc.subjectExperiment design
dc.subjectHigh-k/metal gates
dc.subjectNoise parameters
dc.subjectOptimum parameters
dc.subjectProcess parameters
dc.subjectTungsten silicide
dc.subjectAnalysis of variance (ANOVA)
dc.titleDesign and optimization of 22 nm gate length high-k/metal gate NMOS transistoren_US
dc.typeConference paperen_US
dspace.entity.typePublication
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