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Application of Taguchi method in the optimization of process variation for 32nm CMOS technology

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dc.citedby10
dc.contributor.authorElgomati H.A.en_US
dc.contributor.authorMajlis B.Y.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorHamid F.A.en_US
dc.contributor.authorZaharim A.en_US
dc.contributor.authorApte P.R.en_US
dc.contributor.authorid36536722700en_US
dc.contributor.authorid6603071546en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid36239165300en_US
dc.contributor.authorid6603573875en_US
dc.contributor.authorid15119466900en_US
dc.contributor.authorid55725529100en_US
dc.date.accessioned2023-12-28T07:05:48Z
dc.date.available2023-12-28T07:05:48Z
dc.date.issued2011
dc.description.abstractIn this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determined by Taguchi method in experimental design. The influence of the main process parameters on threshold voltage were determined using analysis of variance (ANOVA). The fabrication processes of the transistor were performed by a simulator namely ATHENA. The electrical characterization of the device was done by the a simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing process parameters. The other two parameter used in this experiments were Source/Drain (S/D) implantation dose and, silicide annealing temperature Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of 0.10308V and -0.10319V for NMOS and PMOS respectively. As conclusion, by utilizing Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.103V that is well within ITRS prediction for 32nm transistor.en_US
dc.description.natureFinalen_US
dc.identifier.epage355
dc.identifier.issue7
dc.identifier.scopus2-s2.0-79960517117
dc.identifier.spage346
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-79960517117&partnerID=40&md5=b54a71cbe95e2ac50dbefd10daf00887
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29610
dc.identifier.volume5
dc.pagecount9
dc.sourceScopus
dc.sourcetitleAustralian Journal of Basic and Applied Sciences
dc.subjectCompensation implantation
dc.subjectHALO
dc.subjectS/D implantation
dc.subjectSilicon MOSFET 32nm
dc.subjectTaguchi method
dc.subjectThreshold voltage
dc.titleApplication of Taguchi method in the optimization of process variation for 32nm CMOS technologyen_US
dc.typeArticleen_US
dspace.entity.typePublication
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