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Characterization and optimizations of silicide thickness in 45nm pMOS device

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dc.citedby4
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorHamid F.A.en_US
dc.contributor.authorZaharim A.en_US
dc.contributor.authorid36239165300en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid6603573875en_US
dc.contributor.authorid15119466900en_US
dc.date.accessioned2023-12-28T07:17:53Z
dc.date.available2023-12-28T07:17:53Z
dc.date.issued2010
dc.description.abstractThe characteristics of high performance 45nm pMOS devices based on International Technology Roadmap for Semiconductor (ITRS) have been studied using ATHENA and ATLAS's simulator. There are four factors were varied for 3 levels to perform 9 experiments. The factors are halo implantation, Source/Drain (S/D) implantation, oxide growth temperature and silicide anneal temperature. In this paper, Taguchi Method was used to analyze the experimental data in order to get the optimum solutions for these factors. The silicide on the poly-Si gate electrode has been used to reduce the gate electrode resistance. The result shows that the threshold voltage (VTH) value is -0.1501 Volts. The value is exactly same with ITRS prediction. This shows that Taguchi Method is a very useful tool to predict the optimum solution in finding the 45nm pMOS fabrication recipes with appropriate VTH value. The result also shows that the average of silicide thickness after optimizations approaches is 30.12nm. �2010 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo5503054
dc.identifier.doi10.1109/ICEDSA.2010.5503054
dc.identifier.epage304
dc.identifier.scopus2-s2.0-77955297325
dc.identifier.spage300
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-77955297325&doi=10.1109%2fICEDSA.2010.5503054&partnerID=40&md5=44e1abb946199d0e2cfd7a60b4738e59
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29649
dc.pagecount4
dc.sourceScopus
dc.sourcetitle2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings
dc.subject45nm pMOS
dc.subjectCobalt salicide
dc.subjectOptimization
dc.subjectTaguchi method
dc.subjectCobalt
dc.subjectCobalt compounds
dc.subjectOptimization
dc.subjectPolysilicon
dc.subjectSemiconductor devices
dc.subjectSemiconductor growth
dc.subjectSilicides
dc.subjectTaguchi methods
dc.subjectThermoelectric equipment
dc.subject45nm pMOS
dc.subjectAnneal temperatures
dc.subjectCobalt salicide
dc.subjectExperimental data
dc.subjectGate electrode resistance
dc.subjectHalo implantation
dc.subjectInternational Technology Roadmap for Semiconductors
dc.subjectOptimum solution
dc.subjectOxide growth
dc.subjectPMOS devices
dc.subjectPoly-si gates
dc.subjectElectron devices
dc.titleCharacterization and optimizations of silicide thickness in 45nm pMOS deviceen_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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