Publication:
Enabling multithreading executions on the XILINX microkernel with a hardware scheduler

Simple item page
dc.citedby0
dc.contributor.authorHarmin Y.S.en_US
dc.contributor.authorJidin R.en_US
dc.contributor.authorMoubark A.M.en_US
dc.contributor.authorZainol M.A.en_US
dc.contributor.authorid24733821700en_US
dc.contributor.authorid6508169028en_US
dc.contributor.authorid57213150847en_US
dc.contributor.authorid57207534385en_US
dc.date.accessioned2023-12-29T07:56:37Z
dc.date.available2023-12-29T07:56:37Z
dc.date.issued2008
dc.description.abstractMultithreading programming can improve performance of an application especially to reduce processor busy waiting. Typically, threads that have to wait for input/output responses can wait in a queue (sleep queue), allowing other threads to utilize processor, therefore improving system timeliness and throughput. As such an application can be partitioned into several threads that can be executed on either single or multiple processors. Sharing of processors among threads however requires scheduling to ensure fair sharing scheme or to meet a specific execution objective. The scheduling mechanism serves to allocate which threads get to run on a processor alternately according to the adopted sharing scheme. Processor can be relieved of executing the required scheduling task if it can be performed by a hardware entity such as Field Programmable Gate Array (FPGA). This paper describes initial design of hardware scheduler and modification of thread manager to support the migration (of thread scheduler into the hardware). The scheduler is designed as an Intellectual Property (IP) core that can be instantiated like any peripheral core. The work is intended to enable multithreading on XILINX microkernel with a hardware thread scheduler instead of Von Neumann stored instruction scheduling execution. �2008 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo4786727
dc.identifier.doi10.1109/ICED.2008.4786727
dc.identifier.scopus2-s2.0-63649121178
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-63649121178&doi=10.1109%2fICED.2008.4786727&partnerID=40&md5=8dfc751b65cbc62a8146b8d629785d6f
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/30958
dc.sourceScopus
dc.sourcetitle2008 International Conference on Electronic Design, ICED 2008
dc.subjectField programmable gate arrays (FPGA)
dc.subjectHardware
dc.subjectScheduling
dc.subjectFair sharing
dc.subjectHardware threads
dc.subjectImproving systems
dc.subjectInitial designs
dc.subjectInput/output
dc.subjectInstruction scheduling
dc.subjectIntellectual property cores
dc.subjectMultiple processors
dc.subjectMultithreading
dc.subjectScheduling mechanisms
dc.subjectScheduling tasks
dc.subjectSharing schemes
dc.subjectMultitasking
dc.titleEnabling multithreading executions on the XILINX microkernel with a hardware scheduleren_US
dc.typeConference paperen_US
dspace.entity.typePublication
Files
Collections
SCOPUS