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VHDL implementation for measurement of the distance test distribution pattern of the Tri-Axial magnetic probe for the PD detection circuit system by using 3 GHz ADC and FPGA

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dc.citedby1
dc.contributor.authorEmillianoen_US
dc.contributor.authorChakrabarty C.K.en_US
dc.contributor.authorGhani A.B.A.en_US
dc.contributor.authorRamasamy A.K.en_US
dc.contributor.authorid35974769600en_US
dc.contributor.authorid6701755282en_US
dc.contributor.authorid24469638000en_US
dc.contributor.authorid16023154400en_US
dc.date.accessioned2023-12-29T07:45:21Z
dc.date.available2023-12-29T07:45:21Z
dc.date.issued2012
dc.description.abstractThis paper is purely a model to implement Partial Discharge (PD) detection in FPGA technology and then implement the VHDL modeled in FPGA technology for measurement of the distance test distribution pattern of the Tri-Axial magnetic probe using 3GHz ADC (ADC083000RB-Reference Board) and impulse generator. Partial discharge (PD) is a well known phenomenon that causes insulation degradation in cross linked polyethylene (XLPE) power cable and ultimately it will cause insulation failure. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA-Xilinx Virtex 5 ML501 Board) for the detection and counting of partial discharge signals in high voltage underground cable. The impulse signals at the input data have very fast rise time in the field can have a bandwith of about 200 - 600 MHz. The output signals of the combination 4 blocks (peak detector block, 64 bit BCD counter with reset block, reset automatic block and 64 bit BCD counter) is processed using reset automatic block and 64 bit latch block for keep output data in LCD to constant when the 64 bit BCD counter block is reset and return to zero again until update new data again. The combination of all blocks of PD detection circuit system is tested by using Xilinx ISE simulator and implemented by ISE Xilinx Synthesized Technology and Xilinx ISE Implement Design. The distance resolution measurement of magnetic field is shown in this paper. � 2011 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo6497711
dc.identifier.doi10.1109/ICUEPES.2011.6497711
dc.identifier.scopus2-s2.0-84876858995
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84876858995&doi=10.1109%2fICUEPES.2011.6497711&partnerID=40&md5=824bb2149c22b03b7a0eb9f6d5fd5a72
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/30188
dc.sourceScopus
dc.sourcetitleProceedings of the 2011 International Conference and Utility Exhibition on Power and Energy Systems: Issues and Prospects for Asia, ICUE 2011
dc.subject64 Bit BCD Counter with Reset Block
dc.subject64 Bit Latch Block
dc.subjectADC with Peak Detector Block
dc.subjectFPGA Simulation
dc.subjectFPGA Technology
dc.subjectPartial Discharge Detection
dc.subjectReal Time Processing
dc.subjectReset Automatic Block
dc.subjectUnderground Cable
dc.subjectVHDL Programming
dc.subjectCables
dc.subjectComputer hardware description languages
dc.subjectDetectors
dc.subjectExhibitions
dc.subjectField programmable gate arrays (FPGA)
dc.subjectPartial discharges
dc.subjectProbes
dc.subjectTechnology
dc.subjectUnderground cables
dc.subject64 Bit BCD Counter with Reset Block
dc.subject64 Bit Latch Block
dc.subjectFPGA technology
dc.subjectPartial discharge detection
dc.subjectPeak detectors
dc.subjectRealtime processing
dc.subjectReset Automatic Block
dc.subjectSignal detection
dc.titleVHDL implementation for measurement of the distance test distribution pattern of the Tri-Axial magnetic probe for the PD detection circuit system by using 3 GHz ADC and FPGAen_US
dc.typeConference paperen_US
dspace.entity.typePublication
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