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Development of process parameters for 22 nm PMOS using 2-D analytical modeling

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dc.citedby1
dc.contributor.authorMaheran A.H.A.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorShaari S.en_US
dc.contributor.authorFaizah Z.A.N.en_US
dc.contributor.authorid36570222300en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid6603595092en_US
dc.contributor.authorid56395444600en_US
dc.date.accessioned2023-05-29T06:00:28Z
dc.date.available2023-05-29T06:00:28Z
dc.date.issued2015
dc.description.abstractThe complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I LEAK ) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO 2 ) and tungsten silicide (WSi x ). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I LEAK where the maximum predicted I LEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/?m. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in I LEAK mean value of 3.96821 nA/?m where is far lower than the predicted value. � 2015 AIP Publishing LLC.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo30007
dc.identifier.doi10.1063/1.4915157
dc.identifier.scopus2-s2.0-84988304504
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84988304504&doi=10.1063%2f1.4915157&partnerID=40&md5=6c4ed198e97335efe62341b7d946451d
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/22360
dc.identifier.volume1657
dc.publisherAmerican Institute of Physics Inc.en_US
dc.sourceScopus
dc.sourcetitleAIP Conference Proceedings
dc.titleDevelopment of process parameters for 22 nm PMOS using 2-D analytical modelingen_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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