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Reusable data-path architecture for encryption-then-authentication on FPGA

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dc.citedby3
dc.contributor.authorAbbas Y.A.en_US
dc.contributor.authorJidin R.en_US
dc.contributor.authorJamil N.en_US
dc.contributor.authorZaba M.R.en_US
dc.contributor.authorid56417806700en_US
dc.contributor.authorid6508169028en_US
dc.contributor.authorid36682671900en_US
dc.contributor.authorid24726154700en_US
dc.date.accessioned2023-05-29T06:13:48Z
dc.date.available2023-05-29T06:13:48Z
dc.date.issued2016
dc.description.abstractThis paper proposes reusable data-path architecture for lightweight cryptography algorithms, reusing some similar hardware components for both encryption and authentication. In addition to efforts by many researches to optimize hardware architectures, to reduce hardware resources, our proposal is to reuse identical functional blocks within crypto-algorithms targeting for more secure cryptography like Message Authentication Code (MAC), authenticated encryption such as Encrypt-then-MAC (EtM) on Field Programmable Gate Arrays (FPGA). For this proposed reusable data-path, we have chosen LED algorithm for encryption and then PHOTON to generate the MAC code. Instead of creating two different circuits, one for PHOTON and another for LED, our proposal�s is to reuse some of identical block functions repeatedly, therefore reduce the size of required circuit area. Reuse of resources or identical functions however require controllers that enable sharing of data path that can also has different �rounds� of transforms required for different modes either PHOTON or LED in this case, in addition to controllers for individual algorithm. Also to enable comparable computation speed, the data-path has to be further refined, an improvement needed at least on par or better than the current techniques. For PHOTON data-path, we have improved performance of Mix-Columns, focusing on lengthy clock cycle of Galois polynomial multiplication. The results show that this proposed EtM hardware architecture achieves significant improvements, up to 587 MHz, 1336 Mbps and 3.2 Mbps/slices, for maximum frequency, throughput and efficiency, respectively. � 2016 Praise Worthy Prize S.r.l. - All rights reserved.en_US
dc.description.natureFinalen_US
dc.identifier.doi10.15866/irecos.v11i1.8367
dc.identifier.epage63
dc.identifier.issue1
dc.identifier.scopus2-s2.0-84964207167
dc.identifier.spage56
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84964207167&doi=10.15866%2firecos.v11i1.8367&partnerID=40&md5=4c872127eaba275d74778cdda032d5da
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/22970
dc.identifier.volume11
dc.publisherPraise Worthy Prizeen_US
dc.sourceScopus
dc.sourcetitleInternational Review on Computers and Software
dc.titleReusable data-path architecture for encryption-then-authentication on FPGAen_US
dc.typeArticleen_US
dspace.entity.typePublication
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