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Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage

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dc.citedby12
dc.contributor.authorElgomati H.A.en_US
dc.contributor.authorMajlis B.Y.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorHamid F.A.en_US
dc.contributor.authorZaharim A.en_US
dc.contributor.authorMohamad T.Z.en_US
dc.contributor.authorApte P.R.en_US
dc.contributor.authorid36536722700en_US
dc.contributor.authorid6603071546en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid36239165300en_US
dc.contributor.authorid6603573875en_US
dc.contributor.authorid15119466900en_US
dc.contributor.authorid53064272300en_US
dc.contributor.authorid55725529100en_US
dc.date.accessioned2023-12-28T07:05:48Z
dc.date.available2023-12-28T07:05:48Z
dc.date.issued2011
dc.description.abstractThis paper explains our investigation of the effect on 32 nm PMOS device threshold voltage (VTH) by four process parameters, namely HALO implantation, Source/Drain (S/D) implantation dose, compensation implantations, and silicide annealing time. Taguchi method determines the setting of process parameters in experimental design while analysis of variance (ANOVA) determines the influence of the main process parameters on threshold voltage. The fabrication processes of the transistor were performed by ATHENA fabrication simulator, while the electrical characterization of the device was done by an ATLAS characterization simulator. These two simulators were combined and the results were analyzed by Taguchi's method in order to aid in design and optimizing process parameters. Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of -0.10319 V is achieved for a 32 nm PMOS transistor. In conclusion, by utilizing Taguchi's method to analyze the effect of process parameters, we can adjust threshold voltage (VTH) for PMOS to a stable value of -0.10319 V that is well within ITRS prediction for a 32 nm PMOS transistor. � 2011 Academic Journals.en_US
dc.description.natureFinalen_US
dc.identifier.epage2379
dc.identifier.issue10
dc.identifier.scopus2-s2.0-80053909219
dc.identifier.spage2372
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-80053909219&partnerID=40&md5=3b1b0cbdd22ba4d8b2dcd6e0798b7821
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29607
dc.identifier.volume6
dc.pagecount7
dc.sourceScopus
dc.sourcetitleInternational Journal of Physical Sciences
dc.subject32 nm PMOS device
dc.subjectCompensation implantation
dc.subjectHALO
dc.subjectS/D implantation
dc.subjectTaguchi's method
dc.subjectThreshold voltage
dc.titleStatistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltageen_US
dc.typeArticleen_US
dspace.entity.typePublication
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