Publication:
Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method

Simple item page
dc.citedby0
dc.contributor.authorElgomati H.A.en_US
dc.contributor.authorMajlis B.Y.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorid36536722700en_US
dc.contributor.authorid6603071546en_US
dc.contributor.authorid12792216600en_US
dc.date.accessioned2023-12-28T06:30:10Z
dc.date.available2023-12-28T06:30:10Z
dc.date.issued2012
dc.description.abstractThis paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilicon thickness and silicide annealing time. The setting of process parameters were determined by Taguchi method L18 experimental design. From there, the level of importance of each of the process parameters on threshold voltage was determined using analysis of variance (ANOVA). Transistor fabrication was performed by using Silvaco ATHENA module. Silvaco ATLAS module takes care of electrical characterization for the device. These two simulators results were analyzed with Taguchi method to aid in design and optimizing process parameters. Threshold voltage (VTH) results were used as the evaluation parameters. The results show that the VTH value 0.1099 V for NMOS can be achieved respectively, much closer to the ITRS prediction than our previous L9 experiment result. As the conclusion, by utilizing L18 Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.1099 V that is well within ITRS 2003 prediction for 32nm transistor � 2012 American Institute of Physics.en_US
dc.description.natureFinalen_US
dc.identifier.doi10.1063/1.4757531
dc.identifier.epage549
dc.identifier.scopus2-s2.0-84874145255
dc.identifier.spage543
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84874145255&doi=10.1063%2f1.4757531&partnerID=40&md5=d67ee74b60a32de8c7844f54df510605
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/29472
dc.identifier.volume1482
dc.pagecount6
dc.sourceScopus
dc.sourcetitleAIP Conference Proceedings
dc.subjectCompensation Implantation
dc.subjectHALO
dc.subjectS/D implantation
dc.subjectSilicon MOSFET 32nm
dc.subjectTaguchi L18
dc.subjectTaguchi Method
dc.subjectThreshold voltage
dc.titleModeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi methoden_US
dc.typeConference paperen_US
dspace.entity.typePublication
Files
Collections
SCOPUS