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A feasible alternative to fdsoi and finfet: Optimization of w/la2o3/si planar pmos with 14 nm gate-length

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dc.citedby2
dc.contributor.authorMah S.K.en_US
dc.contributor.authorKer P.J.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorZainul Abidin N.F.en_US
dc.contributor.authorAli Gamel M.M.en_US
dc.contributor.authorid57191706660en_US
dc.contributor.authorid37461740800en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid57210155462en_US
dc.contributor.authorid57280351300en_US
dc.date.accessioned2023-05-29T09:05:50Z
dc.date.available2023-05-29T09:05:50Z
dc.date.issued2021
dc.descriptionCost effectiveness; Fins (heat exchange); Gate dielectrics; Graphene; High-k dielectric; Low-k dielectric; Silica; Silicon on insulator technology; Silicon oxides; Silicon wafers; Threshold voltage; Voltage scaling; Feasible alternatives; Fin field-effect transistors; Fully depleted silicon-on-insulator; Gate-length; MOS-FET; MOSFETs; Performance; PMOS; Taguchi; Technology nodes; FinFETen_US
dc.description.abstractAt the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore�s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using La2O3 as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters� variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage (Vth) of ?0.289 V � 12.7% and Ioff of less than 10?7 A/�m, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO2 formation at the Si interface and rapid annealing processing are required to achieve La2O3 thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on Vth, Ion and Ioff were investigated. The improved voltage scaling resulting from the lower Vth value is associated with the increased Ioff due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process. � 2021 by the authors. Licensee MDPI, Basel, Switzerland.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo5721
dc.identifier.doi10.3390/ma14195721
dc.identifier.issue19
dc.identifier.scopus2-s2.0-85116104818
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85116104818&doi=10.3390%2fma14195721&partnerID=40&md5=c09fce74d1bd746abf99a2a0e71a00a2
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/25971
dc.identifier.volume14
dc.publisherMDPIen_US
dc.relation.ispartofAll Open Access, Gold, Green
dc.sourceScopus
dc.sourcetitleMaterials
dc.titleA feasible alternative to fdsoi and finfet: Optimization of w/la2o3/si planar pmos with 14 nm gate-lengthen_US
dc.typeArticleen_US
dspace.entity.typePublication
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