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Statistical process modelling for 32nm high-K/metal gate PMOS device

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dc.citedby9
dc.contributor.authorMaheran A.H.A.en_US
dc.contributor.authorNoor Faizah Z.A.en_US
dc.contributor.authorMenon P.S.en_US
dc.contributor.authorAhmad I.en_US
dc.contributor.authorApte P.R.en_US
dc.contributor.authorKalaivani T.en_US
dc.contributor.authorSalehuddin F.en_US
dc.contributor.authorid36570222300en_US
dc.contributor.authorid56395444600en_US
dc.contributor.authorid57201289731en_US
dc.contributor.authorid12792216600en_US
dc.contributor.authorid55725529100en_US
dc.contributor.authorid56989358500en_US
dc.contributor.authorid36239165300en_US
dc.date.accessioned2023-05-16T02:45:42Z
dc.date.available2023-05-16T02:45:42Z
dc.date.issued2014
dc.description.abstractThe evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (VTH) and leakage current (IOFF). The simulation result shows that the optimal value of VTH and IOFF which are 0.1030075V and 3.4264075×10-12A/um respectively are well within ITRS prediction. © 2014 IEEE.en_US
dc.description.natureFinalen_US
dc.identifier.ArtNo6920839
dc.identifier.doi10.1109/SMELEC.2014.6920839
dc.identifier.epage235
dc.identifier.scopus2-s2.0-84908224922
dc.identifier.spage232
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84908224922&doi=10.1109%2fSMELEC.2014.6920839&partnerID=40&md5=5e89c397000155d2e22b534ec7397726
dc.identifier.urihttps://irepository.uniten.edu.my/handle/123456789/21850
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceScopus
dc.sourcetitleIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
dc.titleStatistical process modelling for 32nm high-K/metal gate PMOS deviceen_US
dc.typeConference Paperen_US
dspace.entity.typePublication
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